A Systolic SNN Inference Accelerator and its Co-optimized Software Framework

Guo, Shasha; Wang, Lei; Wang, Shuquan; Deng, Yu; Yang, Zhijie; Li, Shiming; Xie, Zhipeng; Dou, Qi

doi:10.1145/3299874.3317966

Cited by 20 publications

(3 citation statements)

References 16 publications

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“…While SNNs have gathered siginiicant research interest as promising bio-inspired models of computation, only a very few works have been done on SNN hardware accelerators [15,24,38,39,45], particularly array-based accelerators [1,6,23,49,52] due to the fact that the spatiotemporal nature of the spikes make it diicult to design an eicient architecture. Importantly, these limited existing works have primarily focused on feedforward SNNs where there exist very limited works that are capable of executing R-SNNs [2,17,37].…”

Section: R-snn Acceleratorsmentioning

confidence: 99%

“…Importantly, these limited existing works have primarily focused on feedforward SNNs where there exist very limited works that are capable of executing R-SNNs [2,17,37]. For example, [1,23,49,52] introduced a systolic array based accelerator for spiking-CNNs. However, these works are only targeting feedforward networks where eicient method to handle recurrence, which produces tightly-coupled data dependency in both time and space, has not been proposed.…”

Section: R-snn Acceleratorsmentioning

confidence: 99%

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SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks

Lee

Zhang

Xie

et al. 2022

J. Emerg. Technol. Comput. Syst.

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Spiking neural networks (SNNs) are brain-inspired event-driven models of computation with promising ultra-low energy dissipation. Rich network dynamics emergent in recurrent spiking neural networks (R-SNNs) can form temporally-based memory, offering great potential in processing complex spatiotemporal data. However, recurrence in network connectivity produces tightly coupled data dependency in both space and time, rendering hardware acceleration of R-SNNs challenging. We present the first work to exploit spatiotemporal parallelisms to accelerate the R-SNN based inference on systolic arrays using an architecture called SaARSP. We decouple the processing of feedforward synaptic connections from that of recurrent connections to allow for the exploitation of parallelisms across multiple time points. We propose a novel time window size optimization (TWSO) technique, to further explore the temporal granularity of the proposed decoupling in terms of optimal time window size and reconfiguration of the systolic array considering layer-dependent connectivity to boost performance. Stationary dataflow and time window size are jointly optimized to trade-off between weight data reuse and movements of partial sums, the two bottlenecks in latency and energy dissipation of the accelerator. The proposed systolic-array architecture offers a unifying solution to an acceleration of both feedforward and recurrent SNNs, and delivers 4,000X EDP improvement on average for different R-SNN benchmarks over a conventional baseline.

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Section: R-snn Acceleratorsmentioning

confidence: 99%

Section: R-snn Acceleratorsmentioning

confidence: 99%

SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks

Lee

Zhang

Xie

et al. 2022

J. Emerg. Technol. Comput. Syst.

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show abstract

“…Spatial architectures couple PEs in such away that they can exchange intermediate results without having to access a central memory [5]. Typical implementations use either fixed data path connections between the individual PEs (Systolic Arrays) [10] or Networkon-Chips (NoCs) that feature a highly flexible packet-based interconnect [9], [11]. Systolic arrays are excellent for performing convolutions in cases where dataflow is easily predictable, i.e., in low sparsity situations [20].…”

Section: Introductionmentioning

confidence: 99%

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks

Sommer¹,

Özkan²,

Keszöcze³

et al. 2022

Preprint

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Spiking Neural Networks (SNNs) compute in an event-based matter to achieve a more efficient computation than standard Neural Networks. In SNNs, neuronal outputs (i.e. activations) are not encoded with real-valued activations but with sequences of binary spikes. The motivation of using SNNs over conventional neural networks is rooted in the special computational aspects of spike based processing, especially the very high degree of sparsity of neural output activations. Well established architectures for conventional Convolutional Neural Networks (CNNs) feature large spatial arrays of Processing Elements (PEs) that remain highly underutilized in the face of activation sparsity. We propose a novel architecture that is optimized for the processing of Convolutional SNNs (CSNNs) that feature a high degree of activation sparsity. In our architecture, the main strategy is to use less but highly utilized PEs. The PE array used to perform the convolution is only as large as the kernel size, allowing all PEs to be active as long as there are spikes to process. This constant flow of spikes is ensured by compressing the feature maps (i.e. the activations) into queues that can then be processed spike by spike. This compression is performed in runtime using dedicated circuitry, leading to a self-timed scheduling. This allows the processing time to scale directly with the number of spikes. A novel memory organization scheme called memory interlacing is used to efficiently store and retrieve the membrane potentials of the individual neurons using multiple small parallel on-chip RAMs. Each RAM is hardwired to its PE, reducing switching circuitry and allowing RAMs to be located in close proximity to the respective PE. We implemented the proposed architecture on an FPGA and achieved a significant speedup compared to other implementations while needing less hardware resources and maintaining a lower energy consumption.

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A Software-Hardware Co-exploration Framework for Optimizing Communication in Neuromorphic Processor

Wang

Kang

et al. 2020

Communications in Computer and Information Science

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A Systolic SNN Inference Accelerator and its Co-optimized Software Framework

Cited by 20 publications

References 16 publications

SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks

SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks

A Software-Hardware Co-exploration Framework for Optimizing Communication in Neuromorphic Processor

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