A systolic array exploiting the inherent parallelisms of artificial neural networks

Chung, Jihoon; Yoon, Hyunsoo; Maeng, Seungryoul

doi:10.1016/0165-6074(92)90017-2

Cited by 26 publications

(15 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The systolic implementation of artificial neural networks has attracted considerable attention since it provides a means not only for efficient parallel digital realisation of neural networks but also because it allows for a general and unified approach to the design of parallel algorithms and architectures for neural network applications [4], ~141, ~151, ~161, ~171, ~191, ~251, ~261. The systolic implementation of the original Huang's algorithm of Eq.…”

Section: Systolic Implementation O F Neural Network Algorithmsmentioning

confidence: 99%

On systolic general system solution for optimal artificial neural network training

Margaritis

Evans

1994

International Journal of Computer Mathematics

View full text Add to dashboard Cite

show abstract

Section: Systolic Implementation O F Neural Network Algorithmsmentioning

confidence: 99%

On systolic general system solution for optimal artificial neural network training

Margaritis

Evans

1994

International Journal of Computer Mathematics

View full text Add to dashboard Cite

show abstract

“…In addition, the interconnection between the chosen systolic configurations, for implementing a specific network, unavoidably leads to the utilisation of a large number of systolic cells [2]. Hence, from the hardware implementation point of view, the mapping of very large ANNs is prohibited [6].…”

Section: Introductionmentioning

confidence: 99%

“…Digital processing although it appears to be inferior when compared to analog processing in terms of computational density, it has advantages of flexibility in terms of programming for a variety of architectures and learning strategies, as well as simplifying the task of memory retention [19]. Currently there is a strong research interest to implement ANNs in VLSI using digital technology [7, 16, 181. The SAAs have already been proved as a good approach to the parallel implementation of ANNs and suitable for VLSI implementation in digital processors [6,10]. Through this approach the communication problems generated by the highly interconnected neurons can be overcome, while the massive parallelism inherent in the problem can be exploited.…”

Section: Introductionmentioning

confidence: 99%

An efficient approach to mapping large anns onto fixed systolic architectures

Bekakos

Efremides

1998

International Journal of Computer Mathematics

View full text Add to dashboard Cite

One of the best solutions to the communication problems arising in artificial neural networks (ANNs), due to the high interconnectivity of neurons, is achleved through their implementation on systolic array architectures (SAAs). The case of systematical mapping policies from ANNs to SAAs, however, is little explored. In this work, an efficient mapping policy is explored, capable of implementing an ANN on the available fixed systolic array, while it still allows the exploitation of the training pattern pipelined parallelism and remains feasible from the aspect of the hardware implementation cost.

show abstract

“…Therefore, the input of current mirror CMAj receives the current (12) while the input of current mirror CMBj receives the current (13) Current , which is replicated 18 times by current mirror CMM has an arbitrary value as long as it assures that the terms are positive.…”

Section: Circuit Descriptionmentioning

confidence: 99%

“…The first designs "general purpose" hardware accelerators or systems that speed up neural algorithms running on conventional computers [4]- [12]. This kind of hardware allows considerable flexibility in the topology and operations of the neural systems.…”

Section: Introductionmentioning

confidence: 99%

A real-time clustering microchip neural engine

Serrano-Gotarredona

Linares-Barranco

1996

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

This paper presents an analog current-mode VLSI implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the popular ART1 algorithm [1], but has been modified resulting in a more VLSI-friendly algorithm [2], [3] that allows a more efficient hardware implementation with simple circuit operators, little memory requirements, modular chip assembly capability, and higher speed figures. The chip described in this paper implements a network that can cluster 100 binary pixels input patterns into up to 18 different categories. Modular expansibility of the system is directly possible by assembling an N×M array of chips without any extra interfacing circuitry, so that the maximum number of clusters is 18×M and the maximum number of bits of the input pattern is N×100. Pattern classification and learning is performed in 1.8µs, which is an equivalent computing power of 4.4×10 9 connections per second plus connection-updates per second. The chip has been fabricated in a standard low cost 1.6µm double-metal single-poly CMOS process, has a die area of 1cm 2 , and is mounted in a 120-pin PGA package. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, and thus has a true asynchronous digital behavior. Experimental chip test results are available, obtained through digital chip test equipment. Fault tolerance at the system level operation is demonstrated through the experimental testing of faulty chips.

show abstract

A systolic array exploiting the inherent parallelisms of artificial neural networks

Cited by 26 publications

References 3 publications

On systolic general system solution for optimal artificial neural network training

On systolic general system solution for optimal artificial neural network training

An efficient approach to mapping large anns onto fixed systolic architectures

A real-time clustering microchip neural engine

Contact Info

Product

Resources

About