A systolic architecture for elliptic curve cryptosystems

Tsai, Wan-Lin; Wang, Sheng-Jyh

doi:10.1109/icosp.2000.894560

Cited by 3 publications

(1 citation statement)

References 18 publications

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“…Most of the known architectures concern the acceleration of the multiplication process by modifying the elliptic equations by changing the Z coordinate term [4] , or by multiplication scalability [5] ,or by using many serial and parallel Arithmetic units [6] , or using High parallel Karatsuba Multipliers [7] , those based on the Massy-Omura multipliers [8] , or the work based on a hybrid multipliers approach [9] , also some parallel approaches [10] , or the New word level structure [11] , or through the systolic architecture of [12] , or by using the half and add method of [13] , or by parallelizing both the add and double Montgomery algorithms [14] .…”

Section: Hardware Implementationmentioning

confidence: 99%

Reconfigurable Elliptic Curve Crypto-Hardware Over the Galois Field GF(2163)

Bencherif¹,

Bessalah²,

Guessoum³

2009

American J. of Applied Sciences

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Problem statement: In the last decade, many hardware designs of elliptic curves cryptography have been developed, aiming to accelerate the scalar multiplication process, mainly those based on the Field Programmable Gate Arrays (FPGA), the major issue concerned the ability of embedding this strategic and strong algorithm in a very few hardware. That is, finding an optimal solution to the one to many problem: Portability against power consumption, speed against area and maintaining security at its highest level. Our strategy is to hardware execute the ECC algorithm that reposes on the ability of making the scalar multiplication over the GF(2 163 ) in a restricted number of clock cycles, targeting the acceleration of the basic field operations, mainly the multiplication and the inverse process, under the constraint of hardware optimization. Approach: The research was based on using the efficient Montgomery add and double algorithm, the Karatsuba-Offman multiplier and the Itoh-Tsjuii algorithm for the inverse component. The hardware implementation was based upon an optimized Finite State Machine (FSM), with a single cycle 163 bits multiplier and a script generated field squarer. The main characteristics of the design concerned the elimination of the different internal component to component delays, the minimization of the global clocking resources and a strategic separation of the data path from the control part. Results: The working frequency of our design attained the 561 MHz, allowing 161786 scalar multiplications per second, outperforming one of the best state of the art implementations (555 MHz); the other contribution concerns the acceleration of the field inverse scheme with a frequency of 777.341 MHz. Conclusion: The results indicated that using different optimizations at the hardware level improve efficiently the acceleration of the ECC scalar multiplication and the choice of the target circuit gratefully enhances propagation delays and increases frequency.

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