A systolic architecture based GF (2m) multiplier using modified LSD first multiplication algorithm

Many a times Mathematical computations are easier in frequency domain than time domain. Discrete Fourier transform (DFT) is a tool to convert signals from time domain to frequency domain which is widely used mainly in Digital Signal and Image Processing applications. Fast Fourier Transform (FFT) is a method to find DFT in time constraint applications which is affected by number of complex multiplier. In this paper 16-bit DFT using Vedic Multiplier, a high- speed multiplier is proposed with an objective to replace conventional complex multiplier and to decrease computation time. The proposed system is implemented in Virtex-4 FPGA and the results show that FFT using Urdhva Tiryakbhyam algorithm of Vedic multiplier is faster than other methods of DFT

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A systolic architecture based GF (2m) multiplier using modified LSD first multiplication algorithm

Cited by 2 publications

References 10 publications

Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix–Vector Product Approach

Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix–Vector Product Approach

FPGA Implementation of DFT Processor using Vedic Multiplier

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