A systolic accelerator for the iterative solution of sparse linear systems

Melham, R. S.

doi:10.1109/12.42132

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“…[18] adapts this strategy to general sparse matrices by assigning matrix entries to jagged bands. For this approach the time complexity is lower bounded by the dimension of the matrix since both b and Ab are streamed through the PE array.…”

Section: (Chapter 34)mentioning

confidence: 99%

Floating-point sparse matrix-vector multiply for FPGAs

deLorimier

DeHon

2005

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

117

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We also analyze the asymptotic efficiency of our architecture as parallelism scales using a constant rent-parameter matrix model. This demonstrates that our data placement techniques provide an asymptotic scaling benefit. While FPGA performance is attractive, higher performance is possible if we re-balance the hardware resources in FPGAs with embedded memories. We show that sacrificing half the logic area for memory area rarely degrades performance and improves performance for large matrices, by up to 5 times. We also 0 the performance effect of adding custom floating-point using a simple area model to preserve total chip area. Sacrificing logic for memory and custom floating-point units increases single FPGA performance to 5 double precision Gflops. iv Contents Acknowledgements iiiAbstract iv

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Section: (Chapter 34)mentioning

confidence: 99%