A SystemC-Based Design Methodology for Digital Signal Processing Systems

Haubelt, Christian; Falk, Joachim; Keinert, Joachim; Schlichter, Tomás; Streubühr, Martin; Deyhle, Andreas; Hadert, Andreas; Teich, Jürgen

doi:10.1155/2007/47580

Cited by 55 publications

(29 citation statements)

References 16 publications

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“…The same elements and attributes are found in well known system design methodologies and notations such as MARTE UML profile [1] or SysteMoC [2]. This means that developers are not expected to build an additional application model exclusively for the purpose of communication latency evaluation, since most (or all) information can be directly extracted from the development models, documentation and code that they are already producing.…”

Section: Application Modelmentioning

confidence: 98%

Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach

Indrusiak

Ost

Moraes

et al. 2010

2010 8th IEEE International Conference on Industrial Informatics

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The evaluation of communication latency in multiprocessor platforms requires the profiling of the application, the description of the architecture of the platform and of the mapping of application tasks onto processing cores. In this paper, we describe a layered approach that allows application developers to obtain accurate figures for communication latency from an abstract model of the application functionality. A complete separation of concerns is a critical part of this approach, so the major contribution here is the definition of interfaces between different layers: an abstract application model, its executable counterpart, the mapping heuristic and the multiprocessor platform model. Case studies with a realistic application and a NoC-based multiprocessor platform show the potential of the proposed approach using two different system evaluation techniques: simulation and static analysis.

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Section: Application Modelmentioning

confidence: 98%

Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach

Indrusiak

Ost

Moraes

et al. 2010

2010 8th IEEE International Conference on Industrial Informatics

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“…Additionally, Daedalus provides means for performing design space exploration and HW synthesis. SystemCoDesigner [25] is similar to Daedalus, but includes also performance evaluation. This framework allows to implement different MoCs with a library-based approach based on SystemC.…”

Section: Related Workmentioning

confidence: 99%

“…To solve the problem of computing a mapping and a schedule for a KPN application, several authors have proposed to use evolutionary algorithms [21], [25], [24]. We instead, use lightweight heuristics that run in linear time.…”

Section: A Computing a Single Application Schedulementioning

confidence: 99%

Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms

Castrillón

Velásquez²,

Stulova

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Nowadays, most embedded devices need to support multiple applications running concurrently. In contrast to desktop computing, very often the set of applications is known at design time and the designer needs to assure that critical applications meet their constraints in every possible use-case. In order to do this, all possible use-cases, i.e. subset of applications running simultaneously, have to be verified thoroughly. An approach to reduce the verification effort, is to perform composability analysis which has been studied for sets of applications modeled as Synchronous Dataflow Graphs. In this paper we introduce a framework that supports a more general parallel programming model based on the Kahn Process Networks Model of Computation and integrates a complete MPSoC programming environment that includes: compilercentric analysis, performance estimation, simulation as well as mapping and scheduling of multiple applications. In our solution, composability analysis is performed on parallel traces obtained by instrumenting the application code. A case study performed on three typical embedded applications, JPEG, GSM and MPEG-2, proved the applicability of our approach.

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“…To address this problem, we have developed a system-level design approach for WSN systems, utilizing the dynamic data driven applications systems (DDDAS) paradigm [1] jointly with dataflow models of computation. Dataflow models of computation have been used in a wide variety of development environments to aid in the design and implementation of signal processing applications (e.g., see [2,3,4,5,6,7,8,9,10]). …”

Section: Introductionmentioning

confidence: 99%

A system-level design approach for dynamic resource coordination and energy optimization in sensor network platforms

Cho

Sudusinghe

Shen

et al. 2013

2013 Asilomar Conference on Signals, Systems and Computers

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Strict run-time and resource constraints in wireless sensor networks (WSNs) introduce complex design problems that need to be addressed systematically. Recent processor platforms for WSNs have groups of peripheral devices that are used for data sensing and processing. Hardware interrupts are commonly used as an efficient method for handling data acquisition from such peripherals. Dynamic control for multiple interrupts and efficient handling of power consumption on embedded processors are important issues when implementing dynamic, data-driven signal processing applications, where the structure of processing subsystems may need to be adapted at run-time based characteristics of input data and associated operating conditions.To address these issues, we introduce a dataflow-based design approach based on integrating interrupt-based signal acquisition in the context of parameterized synchronous dataflow (PSDF) modeling. This application of PSDF provides a useful foundation for structured development of power-and energy-efficient wireless sensor network systems for dynamic, data-driven applications systems (DDDAS), including DDDAS that employ intensive acquisition and processing of signals from heterogeneous sensors. To demonstrate our proposed new signal-processing-oriented, dataflowbased design approach -which we refer to as DDPSDF (data-driven PSDF) -we have implemented an embedded speech recognition system using the proposed DDPSDF techniques. We demonstrate that by applying our DDPSDF approach, energy-and resource-efficient embedded software can be derived systematically from high level models of DDDAS functional structure.

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A SystemC-Based Design Methodology for Digital Signal Processing Systems

Cited by 55 publications

References 16 publications

Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach

Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach

Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms

A system-level design approach for dynamic resource coordination and energy optimization in sensor network platforms

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