A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs

Bertran, Ramon; Gonzelez, M.; Martorell, Xavier; Navarro, Nacho; Ayguadé, Eduard

doi:10.1109/tc.2012.97

Cited by 68 publications

(75 citation statements)

References 21 publications

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“…The Bottom-up approaches rely on some knowledge of the underlying architecture to produce more reliable and enlightening power models [16,18]. For instance, they can provide a microarchitectural component-wise power consumption breakdown [25].…”

Section: Bottom-up Power Modelsmentioning

confidence: 99%

“…Again, some manual tuning may be needed to improve the accuracy of the model [25], although the model generation can be completely automatized if enough microbenchmarks are defined [16,18].…”

Section: Bottom-up Power Modelsmentioning

confidence: 99%

“…When dealing with OS power-aware policies, this is a very necessary feature in order to guide the OS scheduling. One promising alternative is to build power models based on hardware events that describe the activity that a process is causing within a processor [15,16,17,18]. This has even been evaluated in shared virtualized environments in order to understand better the energy efficiency challenges [6] and to perform power and energy accounting [19,20].…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, the Bottom-up approaches [16,18,25] rely on some knowledge of the underlying architecture to produce more informative, responsive and accurate power models. These approaches are able to breakdown the power components of the architecture but they are more complex to deploy than the Top-down ones.…”

Section: Introductionmentioning

confidence: 99%

“…In the literature, we can find models trained using specifically designed microbenchmarks [15,16,18] or models trained using real applications [36]. The former claim more generality whereas the latter aim to be more accurate for such application domain.…”

Section: Introductionmentioning

confidence: 99%

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Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Bertran

González

Martorell

et al. 2012

The Computer Journal

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Counter-based power models have attracted the interest of researchers because they became a quick approach to know the insights of power consumption. Moreover, they allow to overpass the limitations of measurement devices. In this paper, we compare different Top-down and Bottom-up Counter-based modeling methods. We present a qualitative and quantitative evaluation of their properties. In addition, we study how to extend them to support the currently ubiquitous Dynamic Voltage and Frequency Scaling (DVFS) mechanism. We propose a simple method to generate DVFS agnostic power models from the DVFS specific models. The proposed method is applicable to models generated using any methodology and allows the reduction of the modeling time without affecting the fundamental properties of the models. The study is performed on an 18 DVFS states Intel R Core TM 2 platform using the SPECcpu2006, NAS and LMBENCH benchmark suites. In our testbed, a 6x reduction on the modeling time only increments 1 percentage point on average the error in the predictions.

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Section: Bottom-up Power Modelsmentioning

confidence: 99%

Section: Bottom-up Power Modelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Bertran

González

Martorell

et al. 2012

The Computer Journal

Self Cite

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Modeling power and energy consumption of dense matrix factorizations on multicore processors

Alonso

Dolz

Mayo

et al. 2013

Concurrency and Computation

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SUMMARYIn this paper, we propose a model for the energy consumption of the concurrent execution of three key dense matrix factorizations, with task parallelism leveraged via the Symmetric Multi‐Processing Superscalar (SMPSs) runtime, on a multicore processor. Our model decomposes the power dissipation into the system, static and dynamic components, with the former two being estimated from basic, off‐line experiments. The dynamic power, on the other hand, requires significantly more care, and we introduce a contention‐aware model that accommodates for the variability of power consumption due to memory contention. Experimental results on an Intel Xeon E5504 processor with four cores, using an internal powermeter that samples the power drawn by the mainboard with a frequency of 1 KHz, show the reliability of the energy model for the Cholesky, LU, and QR factorizations on this platform. Copyright © 2013 John Wiley & Sons, Ltd.

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