A systematic analysis of equivalence in multistage networks

Abstract

Abstract-Many approaches to switching in optoelectronic and optical networks decompose the switching function across multiple stages or hops. This paper addresses the problem of determining whether two multistage or multihop networks are functionally equivalent. Various ad-hoc methods have been used in the past to establish such equivalences. A systematic method for determining equivalence is presented based on properties of the link permutations used to interconnect stages of the network. This method is useful in laying out multistage networks, in determining optimal channel assignments for multihop networks, and in establishing the routing required in such networks. A purely graphical variant of the method, requiring no mathematics or calculations, is also described.Index Terms-Multistage interconnection networks, networks, optical interconnections.

Performance evaluation of generic multi-stage interconnection networks with blocking and back-pressure mechanism

“…Networks with 3 to 6 stages with the sizes of 8 × 8, 16 × 16, 32 × 32, and 64 × 64 have been implemented. These basics have been widely used in the previous studies [2][3][4][5]10,12,14,19,21,25]. In simulation runs, it is assumed that the length of the packets is constant and equals to 128 bits.…”

“…It is assumed that the processing speed of the memories at the destination is fast enough, so that the packets do not wait at the buffers of the last stage. Such assumptions are common for the MINs [2][3][4][5]12,14,19,21,25]. For each experiment, simulations have been done for the entire 300,000 cycles.…”

“…This method, changing the bit order, defines the connection pattern between the switches and is expressed as Definition 1 [25] Each Link Permutation (LP) is defined based on bit shuffling as below…”

“…According to [25], there are different permutations for different networks. For instance, Butter f ly(β) in the Butterfly networks is defined as In the above equation, S j and D j represent the jth bit of the source and destination addresses, respectively.…”

“…In this paper, similar to many existing studies [2][3][4][5]12,14,16,21,25], an N × N network is defined that consists of 2 × 2 switches. These 2 × 2 switches can be expanded to k × k dimension.…”