A system-on-chip platform for the internet of things featuring a 32-bit RISC-V based microcontroller

Duran, Ckristian; Rueda, Ernesto; Amaya, Andres; Torres, Rolando; Ardila, Javier; Rueda, D. Luis; Castillo, Giovanny; Agudelo, Anderson; Rojas, Camilo; Chaparro, Luis Carlos Guayacán; Hurtado, Harry; Romero, Juan; Ramirez, Wilmer; Gomez, Hector; Hernández, Humberto Escalante; Roa, Elkim

doi:10.1109/lascas.2017.8126878

Cited by 9 publications

(8 citation statements)

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“…Therefore, the operating frequency in [21] could easily go higher than 500-MHz, while those in [23] and in this work were limited by the general digital I/Os, as seen in the table. For the dynamic power consumption of P Active , the result of this work was measured while running the Dhrystone test, while the result in [23] was measured while running three while loops. Therefore, if the microcontroller in [23] was running the Dhrystone test when being measured, the value of 23.05-W/MHz should be a bit higher.…”

Section: Comparison and Discussionmentioning

confidence: 90%

“…The reason is that for those designs without integrated Phase-Locked Loop (PLL) or Frequency-Locked Loop (FLL), the operating frequencies heavily depended on the I/O circuits. For example, the chip in [21] had integrated FLL while those chips in [23] and in this work had not. Therefore, the operating frequency in [21] could easily go higher than 500-MHz, while those in [23] and in this work were limited by the general digital I/Os, as seen in the table.…”

Section: Comparison and Discussionmentioning

confidence: 94%

“…For example, the chip in [21] had integrated FLL while those chips in [23] and in this work had not. Therefore, the operating frequency in [21] could easily go higher than 500-MHz, while those in [23] and in this work were limited by the general digital I/Os, as seen in the table. For the dynamic power consumption of P Active , the result of this work was measured while running the Dhrystone test, while the result in [23] was measured while running three while loops.…”

Section: Comparison and Discussionmentioning

confidence: 94%

“…For the comparison, Table II gives the results of this work and two other recent 32-bit RISC-V microcontrollers. To provide a better point-of-view, the results of PULPv2 [21] and Duran et al [23] were scaled to the equivalent results of a 65-nm node by using the equations from [30]. It is noted that because the equations in [30] did not have the parameters for the 28-nm process, the scaled values of PULPv2 [21] were calculated by using the settings of the 32-nm process instead.…”

Section: Comparison and Discussionmentioning

confidence: 99%

“…For small low-power energy-efficient 32-bit RISC-V microprocessors, although there were plenty of IP cores presented in FPGAs as reviewed by R. Höller et al in June 2019 [19], silicon proof publications were still limited. The worthmention 32-bit RISC-V chip measurement publications can be listed are the Parallel Ultra-Low Power (PULP) SoC in 2016 [20], PULPv2 SoC in 2017 [21], the low-power microcontroller intended for Internet of Things (IoT) in 2016 [22] and 2017 [23], the FE310-G000 in 2017 [24], and the FE310-G002 in 2019 [25]. In this paper, a 32-bit RISC-V microcontroller is presented and measured.…”

Section: Risc-v Is An Open-source Isa That Was First Presented By Thementioning

confidence: 99%

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Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Hoang

Duran

Nguyen

et al. 2020

IEICE Electron. Express

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In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm 2 of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (V DD) with +1.6-V back-gate bias voltage (V BB). The best power density of 33.4-W/MHz is reached at 0.5-V V DD with +0.8-V V BB. The least current leakage of 3-nA is retrieved at 0.5-V V DD with −2.0-V V BB .

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