A Survey Paper on Design and Implementation for Voltage Drop in CMOS Rectifier

Abstract

This paper presents the study and survey analysis on different width size of transistor in CMOS rectifier for output voltage drop. The paper gives information about miniaturizing the CMOS rectifier using two PMOS and NMOS configuration. This investigation focuses on the effect of the width-to-length ratio by using 0.35µm technology. Therefore, increase the width size and minimize the internal resistance. The model is operated at a frequency of 50Hz with an AC voltage source. CADENCE software is used for simulation and designing work.