A survey of various types of adaptive filters based on the signal and image processing applications

Caroline, B. Elizabeth; Vidhya, J.; Ragasudha, I.

doi:10.1109/icscan49426.2020.9262328

Cited by 1 publication

(1 citation statement)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…During the measurements, the sensor not only detects the heart electrical signals, but also will pick-up noises as the sensors are also sensitive to electric and magnetic fields (EMF), especially the power line noise [4]. To remove those artifacts, the FIR filter is typically used as it has linear phase characteristics and has less distortions as compared to the conventional analogue filter [5,6].…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA

Chessda Uttraphan,

Mohd Izzul Ariffi Ardani,

Chua Wee Heng

et al. 2024

ARASET

View full text Add to dashboard Cite

Electrocardiogram (ECG) signals are commonly used to diagnose heart-related diseases. However, noise induced during the measurement process can affect the accuracy of the diagnosis. Digital filters, such as the Finite Impulse Response (FIR) filter, are widely used to filter out noise from the ECG signal. Nevertheless, the processing speed of software-based FIR filters is slow for large ECG datasets due to serial processing. This paper presents a hardware implementation of the FIR filter for ECG signal processing to overcome the processing speed issue. The filter is designed using the Kaiser Window method and implemented on the Intel Cyclone IV Field Programmable Gate Array (FPGA). The filter is first designed in MATLAB to obtain the filter coefficients where the ECG data were obtained from Physionet database. From the difference equation, we designed the signal flow graph (SDFG) and then mapped into hardware logics to enable parallel processing. Simulation results of the software (MATLAB) and hardware (FPGA) implementations are obtained and compared. The results show that the FPGA-based FIR filter can process the ECG signal up to 1,250 times faster than software implementations. To further optimize the design and reduce hardware cost, we introduce optimized designs by applying the operation scheduling and constrained resource allocation techniques. The maximum operating frequency, logic utilization, and power consumption of each design were analysed and compared. This study demonstrates that custom-designed hardware logic for digital signal processing can significantly outperform software implementations due to its parallel processing capabilities. The proposed optimization techniques reduce the hardware cost while maintaining high processing speed and accuracy. The hardware implementation of the FIR filter for ECG signal processing has numerous applications in diagnosing heart-related diseases and real-time monitoring of ECG signals in critical care settings.

show abstract

Section: Introductionmentioning

confidence: 99%