A Survey of Performance Modeling and Simulation Techniques for Accelerator-Based Computing

Lopez-Novoa, Unai; Mendiburu, Alexander; Miguel-Alonso, José

doi:10.1109/tpds.2014.2308216

Cited by 50 publications

(40 citation statements)

References 54 publications

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“…Performance models should generate reports of performance from input applications ported into a specific device. Some researchers [11] identify the modeling performance of parallel systems into three main approaches: Analytical modeling [18] form a set of equations represent most of system characteristics in mathematical way and compare results of different sets' equations. Machine Learning [19] imply artificial intelligence in the performance modeling task by machinery studying the relations and behavioral of systems and eventify assemble some new valuable information.…”

Section: Modeling Methodologymentioning

confidence: 99%

“…Accelerators can be classified into: GPUs and many-cores such as Intel's Xeon Phi coprocessor [10]. Other approaches like Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs) [11]. GPUs are programmable computational accelerators that aim to accelerate a wide range of parallel applications [12], composed of a set of processing cores and a memory hierarchy.…”

Section: A Accelerators and Heterogeneous Architecturesmentioning

confidence: 99%

“…The Intel Xeon Phi accelerator is the second-generation product of these family, designed based on the concept of Many Integrated Core (MIC) architecture which basically means a combination of many CPU cores grouped over a single chip [13]. And the memory space will be shared between the GPUs and CPUs which reduced the expenses of the older accelerators where they used to use independence memory space each [11].…”

Section: A Accelerators and Heterogeneous Architecturesmentioning

confidence: 99%

“…Different methods can generate application matrixes [11] like Analysis of the source code, analysis of an intermediate representation (IR) and disassembling the final binary files.…”

Section: Characterizing Applicationsmentioning

confidence: 99%

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A study of recent contributions on performance and simulation techniques for accelerator devices

Ajam

Agyeman

2017

2017 4th International Conference on Electrical and Electronic Engineering (ICEEE)

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Abstract-High performance computing platform is moving from homogeneous individual unites to heterogeneous systems. Where each unit is a combination of homogeneous cores and accelerator devices. Accelerator such as GPUs, FPGAs, DSPs, these devices usually designed for the specific and intensive type of computing tasks. The presence of these devices have created fresh and attractive development platforms for developers and designers, brand new performance analysis frameworks and optimization tools. This is the cutting edge in the performance of some accelerator devices like GPUs and Intel's Xeon Phi. We outline some of the existing heterogeneous systems and their development frameworks. The core of this study is a review of performance modeling of these devices. In this paper, we address the emerging issues that affect the performance of these devices and associated techniques employed for simulation and evaluation.

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Section: Modeling Methodologymentioning

confidence: 99%

Section: A Accelerators and Heterogeneous Architecturesmentioning

confidence: 99%

Section: A Accelerators and Heterogeneous Architecturesmentioning

confidence: 99%

“…Different methods can generate application matrixes [11] like Analysis of the source code, analysis of an intermediate representation (IR) and disassembling the final binary files.…”

Section: Characterizing Applicationsmentioning

confidence: 99%

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A study of recent contributions on performance and simulation techniques for accelerator devices

Ajam

Agyeman

2017

2017 4th International Conference on Electrical and Electronic Engineering (ICEEE)

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“…A survey of performance modeling techniques is given in [20]. According to it, three main approaches for performance modeling can be found in the literature: analytical modeling, machine learning and simulation.…”

Section: Existing Work On Performance Predictionmentioning

confidence: 99%

A novel global methodology to analyze the embeddability of real-time image processing algorithms

Saussard

Bouzid

Vasiliu

et al. 2017

J Real-Time Image Proc

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Advanced driver assistance systems applications increasingly use cameras and image processing algorithms. To embed and achieve real-time execution of these algorithms, semiconductor companies propose heterogeneous systems-on-chip (SoCs). Embedding algorithms on this type of hardware is not trivial: One needs to determine how to partition the computational load on the different processing units. In addition, it is not easy to predict whether a given algorithm can be executed on a given heterogeneous SoC while meeting real-time constraints. We propose a novel global methodology to assist with embedding image processing algorithms on heterogeneous SoC while meeting realtime constraints (using a soft real-time analysis). Our approach proposes several heuristics predicting delays and execution times and is based on a set of multi-level test vectors which extract key features of heterogeneous architectures.

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Stepwise‐refinement for performance: a methodology for many‐core programming

Hijma

Nieuwpoort

Jacobs

et al. 2015

Concurrency and Computation

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Many-core hardware is targeted specifically at obtaining high performance, but reaching high performance is often challenging because hardware-specific details have to be taken into account. Although there are many programming systems that try to alleviate many-core programming, some providing a high-level language, others providing a low-level language for control, none of these systems have a clear and systematic methodology as a foundation. In this article, we propose stepwise-refinement for performance: a novel, clear, and structured methodology for obtaining high performance on many-cores. We present a system that supports this methodology, offers multiple levels of abstraction to provide programmers a trade-off between highlevel and low-level programming, and provides programmers detailed performance feedback. We evaluate our methodology with several widely varying compute kernels on two different many-core architectures: a Graphical Processing Unit (GPU) and the Xeon Phi. We show that our methodology gives insight in the performance, and that in almost all cases, we gain a substantial performance improvement using our methodology.Section 2 elaborates how various many-core programming approaches relate to MCL. In Section 3, we introduce our methodology stepwise-refinement for performance. Section 4 gives an overview of MCL and how our system implements our methodology. In Section 5, we give a detailed example of how the process of stepwise-refinement for performance takes place. Section 6 discusses several of the implementation techniques of our system. Section 7 evaluates our techniques for various well-known compute kernels. We conclude the article with a discussion and conclusion. RELATED WORKThe challenges in many-core programming are widely recognized, and there are many approaches that try to alleviate it. This following section discusses the current status of programming manycores and identifies issues (summarized in Table I) that we try to address in our work. We distinguish three programming approaches: high-level programming, separation of concerns, and a tuning cycle approach. Section 2.2 discusses systems that influenced MCL. STEPWISE-REFINEMENT FOR PERFORMANCE 4517 2.1.3. Tuning cycle approach. The tuning cycle approach is an iterative process that usually consists of the following steps: evaluate the performance of an application, analyze the gathered results, and refactor the code to increase the performance. This approach usually fits low-level languages such as CUDA [28] or OpenCL [29] that offer programmers high degrees of control over the code. However, it can also be applied to directive-based programming systems, where in each step, more detailed directives are inserted [30][31][32][33][34][35]. Figure 15. Part of the hardware description mic. Xeon PhiMic. Intel's Many Integrated Core (MIC) architecture contains several tens of in-order x86 cores with powerful vector units and several hardware threads connected through a ring network. The MIC exposes two layers of parallelism: vector in...

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A Survey of Performance Modeling and Simulation Techniques for Accelerator-Based Computing

Cited by 50 publications

References 54 publications

A study of recent contributions on performance and simulation techniques for accelerator devices

A study of recent contributions on performance and simulation techniques for accelerator devices

A novel global methodology to analyze the embeddability of real-time image processing algorithms

Stepwise‐refinement for performance: a methodology for many‐core programming

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