A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities

Abstract

Graph convolutional networks (GCNs) based on convolutional operations have been developed recently to extract high-level representations from graph data. They have shown advantages in many critical applications, such as recommendation system, natural language processing, and prediction of chemical reactivity. The problem for the GCN is that its target applications generally pose stringent constraints on latency and energy efficiency. Several studies have demonstrated that field programmable gate array (FPGA)-based GCNs accelerators, which balance high performance and low power consumption, can continue to achieve orders-of-magnitude improvements in the inference of GCNs models. However, there still are many challenges in customizing FPGA-based accelerators for GCNs. It is necessary to sort out the current solutions to these challenges for further research. For this purpose, we first summarize the four challenges in FPGA-based GCNs accelerators. Then we introduce the process of the typical GNN algorithm and several examples of representative GCNs. Next, we review the FPGA-based GCNs accelerators in recent years and introduce their design details according to different challenges. Moreover, we compare the key metrics of these accelerators, including resource utilization, performance, and power consumption. Finally, we anticipate the future challenges and directions for FPGA-based GCNs accelerators: algorithm and hardware co-design, efficient task scheduling, higher generality, and faster development.

A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems

“…Other studies have provided detailed insights into the use of GNNs in various applications such as the Internet of Things (IoT) [55], network science [56], and language processing [57]. There are also general information on accelerators and efficient GNNs [29,58,59]. Liu et al [60] approach current and future GNN work from an algorithmic perspective, while Abadal et al [61] provide a comprehensive overview of the acceleration algorithms and GNN fundamentals.…”

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

“…This theory, along with the concept of abstraction, has guided the semiconductor industry to the present day leading to the emergence of System on Chip (SoC), hybrid scheduling ( Ghavidel, Sedaghat & Naghibzadeh, 2020 ; Aurora Dugo et al, 2022 ), heterogeneous multicore processors ( Pei, Kim & Gaudiot, 2016a ; Krishnakumar et al, 2020 ), and hardware microkernels ( Dantas, De Azevedo & Gimenez, 2019a ), today’s computing systems ( Bae, 2021 ) and Internet of Things (IoT) concepts. With technological development, designers of central processing units have developed modern IC in various forms such as FPGAs ( Li et al, 2022 ), complex programmable logic devices (CPLDs), or application-specific integrated circuits (ASICs), which are faster and smaller, consume less power and, last but not least, are cheaper. In current practical research, they continue to improve the performance of processors, ISAs, and RTOSs by multiplying thread contexts, integrating scheduling algorithms into the hardware, and minimizing the response time for the entire RTS ( Dantas, De Azevedo & Gimenez, 2019b ; Pei, Kim & Gaudiot, 2016b ).…”