A Survey and Taxonomy of FPGA-based Deep Learning Accelerators

Blaiech, Ahmed Ghazi; Khalifa, Khaled Ben; Valderrama, Carlos; Fernandes, Marcelo A. C.; Bedoui, Mohamed Hédi

doi:10.1016/j.sysarc.2019.01.007

Cited by 62 publications

(23 citation statements)

References 16 publications

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“…Different solutions for the acceleration of DNN algorithms include Graphic Processing Unit (GPU) [11], Application Specific Integrated Circuit (ASIC) [12], and Field-Programmable Gate Array (FPGA) [13]. The advantages of GPU-based solutions are programmability and comparatively low cost while providing the high computational power, which is typically required during the training phase of deep learning algorithms.…”

Section: A Related Workmentioning

confidence: 99%

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A Scalable System-on-Chip Acceleration for Deep Neural Networks

et al. 2021

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The size of neural networks in deep learning techniques is increasing and varies significantly according to the requirements of real-life applications. The increasing network size, along with the scalability requirements, poses significant challenges for a high performance implementation of deep neural networks (DNN). Conventional implementations, such as graphical processing units and application specific integrated circuits, are either less efficient or less flexible. Consequently, this article presents a system-on-chip (SoC) solution for the acceleration of DNN, where an ARM processor controls the overall execution and off-loads computational intensive operations to a hardware accelerator. The system implementation is performed on a SoC development board. Experimental results show that the proposed system achieves a speed-up of 22.3, with a network architecture size of 64X64, in comparison with the native implementation on a dual core cortex ARM-A9 processor. In order to generalize the performance of complete system, a mathematical formula is presented which allows to compute the total execution time for any architecture size. The validation is performed by taking Epileptic Seizure Recognition as the target case study. Finally, the results of the proposed solution are compared with various state-of-the-art solutions in terms of execution time, scalability, and clock frequency.

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Section: A Related Workmentioning

confidence: 99%

“…As a result, a large computational time is required. Therefore, some dedicated architectures such as GPUs [11], FPGAs [13] and ASICs [14] are required.…”

Section: A Case Study: Epileptic Seizure Recognitionmentioning

confidence: 99%

A Scalable System-on-Chip Acceleration for Deep Neural Networks

et al. 2021

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“…Deep learning originates from the discussion and exploration of artificial neural network (ANN) and deep neural networks (DNN), and it is a deep machine learning model [ 22 ]. The deep learning executes a series of nonlinear transformation to study how to automatically extract the multilayer characteristics from the original data, and it has been widely applied in the field of image recognition, speech recognition, natural language processing, drug discovery, and so on [ 23 ].…”

Section: Computational Logistics and Deep Learningmentioning

confidence: 99%

Computational Logistics for Container Terminal Handling Systems with Deep Learning

2021

Computational Intelligence and Neuroscience

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Container terminals are playing an increasingly important role in the global logistics network; however, the programming, planning, scheduling, and decision of the container terminal handling system (CTHS) all are provided with a high degree of nonlinearity, coupling, and complexity. Given that, a combination of computational logistics and deep learning, which is just about container terminal-oriented neural-physical fusion computation (CTO-NPFC), is proposed to discuss and explore the pattern recognition and regression analysis of CTHS. Because the liner berthing time (LBT) is the central index of terminal logistics service and carbon efficiency conditions and it is also the important foundation and guidance to task scheduling and resource allocation in CTHS, a deep learning model core computing architecture (DLM-CCA) for LBT prediction is presented to practice CTO-NPFC. Based on the quayside running data for the past five years at a typical container terminal in China, the deep neural networks model of the DLM-CCA is designed, implemented, executed, and evaluated with TensorFlow 2.3 and the specific feature extraction package of tsfresh. The DLM-CCA shows agile, efficient, flexible, and excellent forecasting performances for LBT with the low consuming costs on a common hardware platform. It interprets and demonstrates the feasibility and credibility of the philosophy, paradigm, architecture, and algorithm of CTO-NPFC preliminarily.

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“…The motivation behind deploying such a network on the edge with FPGA is to balance between low power consumption and high performance. Thus, FPGA design of DCNNs has become an active research topic in recent years [18][19][20].…”

Section: Introductionmentioning

confidence: 99%

AlphaGo Policy Network: A DCNN Accelerator on FPGA

Zhu

Gao

et al. 2020

IEEE Access

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The game of GO has long been regarded as the most challenging game for artificial intelligence because of its enormous search space and the difficulty of evaluating its board positions. In early 2016, the defeat of Lee Sedol by AlphaGo became the milestone of artificial intelligence. AlphaGo's success lies in that it efficiently combines policy and value networks with Monte Carlo tree search (MCTS). And these deep convolutional neural networks (DCNNs) are trained by the combination of supervised learning and reinforcement learning. However, large convolution operations are computationally-intensive and typically require a powerful computing platform, for example, a graphics processing unit (GPU). Therefore, it is challenging to apply DCCNs in resource-limited embedded systems. Field programmable gate array (FPGA) is proposed to be an appropriate solution to implement real-time DCCNs models. However, the limited bandwidth and on-chip memory storage are the bottlenecks for DCCNs acceleration. In this paper, an AlphaGo Policy Network is designed, and efficient hardware architectures are proposed to accelerate the DCCN model. The accelerator can be fit into different FPGAs, providing the balancing between processing speed and hardware resources. As an example, the AlphaGo Policy Network is implemented on Xilinx design suite VCU118, and the results show that our implementation achieved a performance of 3036.32 GOPS and achieved up to 56x speedup compared to CPU and 22.4x speedup compared to GPU.

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A Survey and Taxonomy of FPGA-based Deep Learning Accelerators

Cited by 62 publications

References 16 publications

A Scalable System-on-Chip Acceleration for Deep Neural Networks

A Scalable System-on-Chip Acceleration for Deep Neural Networks

Computational Logistics for Container Terminal Handling Systems with Deep Learning

AlphaGo Policy Network: A DCNN Accelerator on FPGA

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