which results in the rapid degradation of organic devices with n-type semiconductors. Several methods have been investigated, such as introducing top-gated device structures [ 12 ] or applying an encapsulation layer on the devices, [ 13,14 ] to prevent the diffusion of water or oxygen into the semiconductors. However, most of the additional layers directly integrated onto the semiconductor usually damage the semiconductor, often causing device failure. [ 15 ] Here, we fabricated a low-voltage organic complementary inverter with a high environmental stability by adopting an ultrathin (typically having a thickness of less than 30 nm) polymer dielectric layer named poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3) via initiated chemical vapor deposition (iCVD). [ 16 ] The pV3D3 exhibited a high fl exibility and a low leakage current ( J i ) less than 10 −9 A cm −2 up to 5 MV cm −1 with an ultralow thickness down to 10 nm. [ 17,18 ] As well as the dielectric layer for electronic devices, a hybrid encapsulation layer via sequential deposition of iCVD and atomic layer deposition (ALD) was applied directly onto the organic complementary inverter to improve the environmental stability of organic electronic devices. [ 19 ] By adopting these dielectric layers and encapsulation layers together, the newly developed organic complementary inverter in this study exhibited a high gain of 130 V/V at a switching threshold voltage ( V M ) of 1.52 V at a supply voltage of 3 V. It also retained high air stability for more than 3 weeks. Also, devices on fl exible substrates were intact up to 2% of tensile strain, demonstrating its excellent mechanical fl exibility.As p-and n-type semiconductors, dinaphtho[2;3-b:2′,3′-f ]-thieno [3,2-b]thiophene (DNTT) and N , N ′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (PTCDI-C13) were selected to fabricate the organic complementary inverters. Prior to the examining the electrical characteristics of the complementary inverters, the electrical characteristics of OTFT with each semiconductor were analyzed ( Figure 1 ). The sub-30 nm-thick iCVD pV3D3 layer was mainly used as a gate dielectric layer in both OTFTs. The use of such an ultrathin polymeric dielectric layer enables the operation of both n-and p-type OTFTs below ±5 V, which is critically important to reduce the power consumption. Furthermore, both p-and n-type OTFTs exhibited hysteresisfree operation with a low gate leakage current ( I G ) in the range of 10 −10 A, demonstrating the excellent performance of the OTFTs with the iCVD dielectric layer. The average µ obtained from ten devices was 0.87 ± 0.19 cm 2 V −1 s −1 for DNTT TFT and 0.71 ± 0.02 cm 2 V −1 s −1 for PTCDI-C13 TFT, respectively. The | V T | of each device was also similar to each other (−1.29 V for