A Supply-Noise-Insensitive Digitally-Controlled Oscillator

Yuan, Chen; Shekhar, Sudip

doi:10.1109/tcsi.2019.2924399

Cited by 16 publications

(5 citation statements)

References 14 publications

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“…A supply-insensitive DCO for ADPLL is proposed by Yuan and Shekhar. 10 The proposed DCO achieves a phase noise of À92 dBc/Hz and power consumption of 2.45 mW which is higher as compared to other designs reported in the literature at an output frequency of 1.25 GHz. The TDC-less and low power ADPLL is proposed by Palaniappan and Siek, 11 which is used in the biomedical implant transreceivers.…”

Section: Adpll Designmentioning

confidence: 81%

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A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

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A dual‐loop ADPLL architecture with 3‐bit flash TDC and background calibration‐based VCO is presented in this paper. The major aim of this work is to achieve the low jitter, low power, fast locking, and PVT‐insensitive ADPLL using simple flash TDC and gain calibrated VCO. A simple flash‐based 3‐bit TDC in the main loop is used which helps in achieving the fast locking with lower power consumption in ADPLL. The novel low phase noise VCO, with gain calibration in another loop, is used to fasten the locking process and jitter reduction due to any PVT variations. Therefore, both flash TDC and dual loop in the proposed ADPLL architecture help in achieving the fast locking. Proposed ADPLL is designed in SCL 180 nm CMOS technology at 1.8 V. The resolution of 3‐bit flash TDC is 3 ps. The achieved jitter of ADPLL is 1.83 ps with a phase noise of −153 dBc/Hz and locking time of 1.7 μs. Total power consumption is 5.3 mW at a frequency of 1.6 GHz.

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Section: Adpll Designmentioning

confidence: 81%

“…The lower locking time of 1.5 μs is achieved by this proposed ADPLL. A supply‐insensitive DCO for ADPLL is proposed by Yuan and Shekhar 10 . The proposed DCO achieves a phase noise of −92 dBc/Hz and power consumption of 2.45 mW which is higher as compared to other designs reported in the literature at an output frequency of 1.25 GHz.…”

Section: Adpll Designmentioning

confidence: 99%

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

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“…To achieve frequency tuning at the output terminal without impacting the overall power consumption, MOS varactors are employed [13].…”

Section: Introductionmentioning

confidence: 99%

A Low Power Hybrid DCO using Three transistor (3-T) XNOR gate, CMOS and Pseudo-NMOS inverter

bagri,

kumar,

kumar

2023

Preprint

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This research article presents a comprehensive investigation of three-bit hybrid-digitally controlled ring oscillator (HDCRO) implemented with TMSC 90nm CMOS technology.The hybrid circuit HDCRO comprises of three distinct delay stages, namely XNOR-based inverter, a CMOS inverter, and a Pseudo-NMOS inverter, all of which have been designed utilizing an inversion MOS varactor (IMOS). Furthermore, the investigation explores the output frequency variation in the load element of the HDCRO by adjusting the capacitance of the digitally controlled MOS varactors. This frequency variation occurs as a result of changing the digital control bits of the MOS varactors at a supply voltage of 0.7 V. The proposed HDCRO demonstrates an oscillation frequency range of 2.558 GHz to 2.649 GHz, with power consumption varying from 3.638 mW to 1.046 mW, and phase noise from -68.070 dB@1 MHz to -67.654 dB@1 MHz relative to the central oscillation frequency. Moreover, by applying a supply voltage variation between 0.5 V and 1 V, a wider frequency tuning range of 1.238 GHz to 4.438 GHz is achieved. This extended tuning range exhibits power consumption variation from 2.785 µW to 54.66 mW, and phase noise from -68.812 dB@1 MHz to -65.445 dB@1 MHz relative to the central oscillation frequency. In summary, this study presents a novel HDCRO architecture that demonstrates excellent performance in terms of frequency range, power consumption and phase noise. The proposed design offers advantages of high speed, low-power and good frequency range; thus has a promising prospect of application in high-performance integrated circuits.

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“…Nevertheless, it is only applicable in the structure with a tail current source. The compensation [9] and cancellation [10] techniques based on characteristics of devices can reject supply noise, which is applicable for circuits with or without the tail current source. However, the power supply rejection capability is achieved in open loop which will introduce additional noise to output directly.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique

Zhou¹,

Ding

Boon

et al. 2021

IEEE Access

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This paper presents a supply-insensitive low-power quadrature local oscillation (LO) generator based on the current-reused voltage-controlled oscillator (VCO) and divide-by-two frequency divider (FD). By utilizing the mutual power-supply rejection (M-PSR) technique, a voltage regulator is embedded into the FD to provide a supply-insensitive voltage for VCO. Meanwhile, the feedback loop provides a supply-insensitive current and time constant compensation for FD. The M-PSR technique does not require extra voltage headroom, thus the proposed quadrature LO generator can work under the supply of 0.9 V. A prototype of the proposed quadrature LO generator is implemented in a 28-nm CMOS process. Measurement results indicate that the LO generator achieves a phase noise of -110.5 dBc/Hz@1MHz at the carrier of 5.9 GHz and the power consumption is 1.8 mW. This work has a competitive figure of merit in supply sensitivity or in area (FOMss or FOMa respectively) among the state-of-the-art works.

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A Supply-Noise-Insensitive Digitally-Controlled Oscillator

Cited by 16 publications

References 14 publications

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

A Low Power Hybrid DCO using Three transistor (3-T) XNOR gate, CMOS and Pseudo-NMOS inverter

A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique

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