A superscalar architecture to exploit instruction level parallelism

Steven, G.B.; Christianson, Bruce; Collins, Roger; Potter, Richard D.; Steven, F.L.

doi:10.1016/s0141-9331(96)01101-5

Cited by 20 publications

(11 citation statements)

References 25 publications

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“…While more details of the architecture can be found elsewhere [3], two further features are directly relevant to this paper. First, all HSA instructions, including branches, may be guarded by one or more Boolean conditions.…”

Section: W R I T E Backmentioning

confidence: 99%

Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture

Egan

Steven²,

Steven³

Proceedings 23rd Euromicro Conference New Frontiers of Information Technology - Short Contributions -

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While delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay mechanism that is more suited to superscalar processors. We then quantitatively compare the performance of our delayed branch mechanism with run-time branch prediction, in the context of a high-performance superscalar architecture that uses aggressive compile-time instruction scheduling. keywords superscalar, delayed branch, branch prediction, instruction scheduling

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Section: W R I T E Backmentioning

confidence: 99%

Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture

Egan

Steven²,

Steven³

Proceedings 23rd Euromicro Conference New Frontiers of Information Technology - Short Contributions -

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show abstract

“…The benchmarks used falls into two categories: the Stanford HSA (Hatfield Superscalar Architecture) benchmarks as described in [4,11,16], recompiled to run on SimpleScalar architecture and the SPEC '95 benchmark programs [10] having as inputs, the files listed in Table 1. The benchmarks were run for maximum 500 millions instructions or to complet ion if they were shorter.…”

Section: P E R F O R M a N C E Evaluations Through Simulationmentioning

confidence: 99%

An alternative to branch prediction

Vintan

Sbera²,

Mihu

et al. 2003

SIGARCH Comput. Archit. News

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Through this paper we developed an alternative approach to the present -day two level dynamic branch prediction structures. Instead of predicting branches based on history information, we propose to pre -calculate the branch outcome. A pre -calculated branch prediction (PCB) determines the outcome of a branch as soon as all of the branch's operands are known. The instruction that produced the last branch's operand will trigger a supplementary branch condition estimation and, after this operation, it correspondingly computes the branch outcome. This outcome is cached into a prediction table. The new proposed PCB algorithm clearly outperforms all the classical branch prediction schemes, simulations on SPEC and Stanford HSA benchmarks, proving to be very efficient. Also, our investigations related to architectural complexity and timing costs are quite optimistic, involving an original alternative to the present-day in branch prediction approach.

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“…The benchmarks were compiled using a C compiler developed at the University of Hertfordshire the HSA (Hatfield Superscalar Architecture) [Ste97]. Instruction traces were then obtained using the HSA instructionlevel simulator, with each trace entry providing information on the branch address, branch type and target address.…”

Section: Benchmark Programsmentioning

confidence: 99%