A Suitability Analysis of Software Based Testing Strategies for the On-line Testing of Artificial Neural Networks Applications in Embedded Devices

Ruospo, Annachiara; Piumatti, D.; Floridia, A.; Sánchez, Ernesto

doi:10.1109/iolts52814.2021.9486704

Cited by 8 publications

(5 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Current state-of-the-art functional methods for detecting faults that may affect AI-powered devices are often based on Software Test Libraries (STLs), a set of assembly programs that can excite and detect faults in the underlying computing device by applying carefully crafted test patterns. However, since STLs require a significant manual effort to develop and may affect the performance of the AI task [22], alternative solutions have been proposed that leverage directly the computations of AI models, such as CNNs. In particular, they involve constructing suitable input data that, when fed to the CNN, can excite faults simply by flowing through the layers of the network and propagate them up to the output layer.…”

Section: B Fault Detection Techniquesmentioning

confidence: 99%

Resiliency Approaches in Convolutional, Photonic, and Spiking Neural Networks

Bosio,

Gomes,

Pavanello

et al. 2024

2024 IEEE 25th Latin American Test Symposium (LATS)

Self Cite

View full text Add to dashboard Cite

show abstract

Section: B Fault Detection Techniquesmentioning

confidence: 99%

Resiliency Approaches in Convolutional, Photonic, and Spiking Neural Networks

Bosio,

Gomes,

Pavanello

et al. 2024

2024 IEEE 25th Latin American Test Symposium (LATS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Algorithmic-based error detection and correction methods using checksum arithmetic are discussed in [13], [26]- [29]. On-line test methods are proposed in [30] based on Software Test Libraries (STL), in [31] based on a simplified metric of dynamic power consumption, and in [32] based on encrypting weights in the memory with an encryption algorithm that spreads single bitflips extending them to multiple bit-flips and checking if the padding bytes used for the encryption to work properly are correctly decrypted.…”

Section: Prior Art On Testing Ai Hardware Acceleratorsmentioning

confidence: 99%

Compact Functional Testing for Neuromorphic Computing Circuits

El-Sayed

Spyrou

Camuñas-Mesa

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

We address the problem of testing Artificial Intelligence (AI) hardware accelerators implementing Spiking Neural Networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the inter-class spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassififed with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modelled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time.

show abstract

“…3) Software-based: In [157], on-line test strategies based on Software Test Libraries (STL) are proposed for embedded systems running ANN applications. STL is composed of selftest routines that are executed during boot-time or run-time.…”

Section: On-line Test 1) Atpg and Functional Testingmentioning

confidence: 99%

“…These solutions bring in new challenges for testing. For instance, in-memory solutions may require understanding and creation Physical-aware DFT [136] DFT overhead Function-aware DFT [134], [135], [145] Complete DFT solutions for large heterogeneous systems Functional test generation [127], [146]- [156] Memory-hungry designs On-line test [157]- [165] New market demands (i.e., 0 DPPM for automotive, on-line test)…”

Section: A Introductionmentioning

confidence: 99%

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

Liu

Stratigopoulos³

2023

IEEE Des. Test

View full text Add to dashboard Cite

In recent years, there has been an expedited trend in embracing bold and radical innovation of computer architectures, aiming at the continuation of computing performance improvement despite the slowed-down physical device scaling. One new frontier in this field focuses on Artificial Intelligence (AI) hardware. While functionality of AI hardware still remains the main focus, testability and dependability of these new architectures need to be addressed before the mainstream adoption. This survey paper covers the state-of-the-art in research and development of dependability and testability solutions for AI hardware including digital or analog implementations of Artificial Neural Networks (ANNs) and Spiking Neural Networks (SNNs), used in accelerators and neuromorphic designs. Trends, challenges and perspectives are also discussed in this paper.

show abstract

A Suitability Analysis of Software Based Testing Strategies for the On-line Testing of Artificial Neural Networks Applications in Embedded Devices

Cited by 8 publications

References 23 publications

Resiliency Approaches in Convolutional, Photonic, and Spiking Neural Networks

Resiliency Approaches in Convolutional, Photonic, and Spiking Neural Networks

Compact Functional Testing for Neuromorphic Computing Circuits

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

Contact Info

Product

Resources

About