A Suggestive Low Power TIQ Comparator Architecture using Adiabatic Logic for Implementation of 3-bit Flash type ADC.

Abstract

Power consumption is prime concern for the designers in modern day scenario. For the devices that are power-driven by tiny rechargeable or non-rechargeable batteries over the entire life period, such as medical transplant devices or portable medical instruments, necessitates lowest possible power consumption. In these devices Analog-to-Digital Converter (ADC) isdynamic component to provide connectionamongstAnalog and Digital system. The paper is aimed to report the design contests and tactics for low power ADCs which are used in biomedical graft devices and instruments. A comparator module of ADCs used in designing of such devices requires more power than other blocks in the device, a low power comparator is suggested for Threshold-Inverter-Quantizer (TIQ)usingDiode-Free-Adiabatic-Logic (DFAL) to implement Flash type ADCs. The projected 3-bit Flash ADC is simulated using Cadence ® Virtuoso IC616 with TSMC 65nm technology. The ADC was simulated atpeak to peak voltage of 1.2V andcapacitive load of 1fF,results in consumption of5.53 µW of average power, which is 66.03 % lesser relative toconservative CMOS-TIQ based comparator. Observed static parameters are: DNL is equal to-0.62 / + 0.57 LSB and INL is equal to- 0.44/ +0.41 LSB.Dynamic parameters observed results are as: THD = -25.25dB, SNR=19.45 dB, SNDR=18.39 dB, ENOB=2.76 bits, SFDR = 23.4 dB.