A Subthreshold Digital Library Using a Dynamic-Threshold Metal-Oxide Semiconductor (DTMOS) and Transmission Gate Logic

Abstract

Sensors and Electron Devices Directorate, ARLApproved for public release; distribution unlimited. ii REPORT DOCUMENTATION PAGE Form Approved OMB No. 0704-0188Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing the burden, to Department of Defense, Washington Headquarters Services, Directorate for Information Operations and Reports (0704-0188), 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. REPORT DATE (DD-MM-YYYY)September 2014 ARL-TN-0635 SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S) SPONSOR/MONITOR'S REPORT NUMBER(S) DISTRIBUTION/AVAILABILITY STATEMENTApproved for public release; distribution unlimited. SUPPLEMENTARY NOTES POC is Romeo Del Rosario and Dr Wilson ABSTRACTA digital library taking advantage of the subthreshold mode of operation is studied and different gate topologies are explored for trade-offs in area, power, and propagation delay. Lowering the supply voltage allows for significant reductions in power consumption due to the squared dependence on voltage in switching logic. Dynamic-threshold metal-oxide semiconductor (DTMOS) inverters were used to improve the speed of inverters and buffers. Transmission gate logic was used to implement arbitrary logic gates to avoid PUN/PDN imbalances of static logic gates in subthreshold. These modifications result in the added benefit of smaller and simpler implementation of XOR/XNOR, making for a more modular nature to implement the common logic gates. The library is used to implement 1-bit full adders and a CIC filter with low power consumption. iii SUBJECT TERMS