A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor

Shi, Linqi; Gai, Weixin; Huang, Jichao; Tang, Liangxiao; Xiang, Xiao

doi:10.1109/iscas.2018.8351292

Cited by 5 publications

(3 citation statements)

References 6 publications

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“…where Δ#, # > , # $%%&'( is the frequency resolution, frequency of reference clock, and frequency offset, respectively, and ℒ"# $%%&'( ) is the corresponding quantization noise [2]. [3] proposes a 10GHz fraction-capacitor-based DCO with the finest frequency resolution of 450kHz. Although its resolution is more than ten times better than conventional scheme, prohibitive area growth keeps it from going further.…”

Section: Introductionmentioning

confidence: 99%

A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer

Yanchi

Gai

Xiang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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A 14GHz digitally controlled oscillator (DCO) is proposed for all-digital phase-locked loop (ADPLL). With a cascade differential-capacitor array, the resolution of DCO is enhanced, which leads to a decrease in quantization noise, while area cost and substrate noise are also significantly reduced. In addition, a resistor-biased DCO output buffer is used to cut down phase noise by eliminating flicker and thermal noise conventional current-mirror structure brings. The proposed DCO is designed in 14nm FinFET process, achieving a phase noise of -110dBc/Hz at 1MHz offset and a frequency resolution of 7kHz. DCO operates in a frequency range of 17.8%, with a 0.017 mm 2 core area. The DCO consumes 6.3mW from a 0.8V supply voltage.

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Section: Introductionmentioning

confidence: 99%

A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer

Yanchi

Gai

Xiang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

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“…The FTW control word which is produced by the frequency controller switches the control pins FTW0 -FTW7 to achieve fine tuning. The equivalent circuit when FTWn is logic '0' and logic '1' is used to derive the capacitance step accomplished for an single fractional capacitor cell [98].…”

Section: Tuning Block Of Dcomentioning

confidence: 99%

“…A minimum available capacitance C in the used 40 nm process and a larger CFn capacitor is utilized to achieve fractional capacitance [97] [98]. Thus in order to obtain a fine capacitance step that tunes the DCO finely, a larger CFn is utilized.…”

Section: Tuning Block Of Dcomentioning

confidence: 99%