2020
DOI: 10.1016/j.mejo.2020.104729
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A sub-harmonic injection locking clock multiplier with FLL PVT calibrator

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Cited by 1 publication
(3 citation statements)
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“…17, according to the Equ. (17). Moreover, the simulated integrated RMS jitter over 10 kHz to 30 MHz before post-layout is reduced from 2.3 ps to 1.1 ps at room temperature, as shown in Fig.…”
Section: Design Of the Proposed Self-aligned Silpllmentioning
confidence: 75%
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“…17, according to the Equ. (17). Moreover, the simulated integrated RMS jitter over 10 kHz to 30 MHz before post-layout is reduced from 2.3 ps to 1.1 ps at room temperature, as shown in Fig.…”
Section: Design Of the Proposed Self-aligned Silpllmentioning
confidence: 75%
“…Hence, the calculated in-band phase noise with the effect of VCDL at the output of PLL can be approximately given by Equ. (17).…”
Section: Phase Noise Analysis Of the Silpll With Self Aligned Injecti...mentioning
confidence: 99%
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