A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-¿ Metal Gate CMOS

Abstract

This paper describes a low-power Intel ® Architecture (IA) processor specifically designed for Mobile Internet Devices (MID) and UltraMobile PCs (UMPC) where average power consumed is in the order of a few hundred mW (as measured by MobileMark'05 OP @ 60 nits brightness) with performance similar to mainstream Ultra-Mobile PCs. The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data L1 caches, independent integer and floating point execution units, ×86 front end execution unit, a 512KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB); a block diagram is shown in Fig. 13.1.1. The design contains 47M transistors in a die size under 25mm 2 manufactured in a 9-metal 45nm CMOS process with optimized transistors for low leakage [1] packaged in a Halide-Free 441 ball, 14×13mm 2 μFCBGA. Thermal Design Power (TDP) consumption is measured at 2W using a synthetic power-virus test at a frequency of 2GHz.Features in this new micro-architecture are selected with low power and high performance per watt efficiency in mind. The pipeline is tailored to execute IA instructions as single atomic operations consisting of a single destination register and up to three source-registers and adheres to the Load-Op-Store instruction format. Further, using power efficient algorithms in areas like instruction decoding and scheduling (traditionally complex circuits that are power hungry) achieves high performance per watt efficiency. In addition, support for Hyper-threading technology (HT) is added; the instruction scheduling logic can find a pair of instructions from either the same thread or across threads in a given cycle to dispatch. HT is a feature that provides high performance per watt (typically 30% increases in performance for a 15% increase in power) efficiency in an in-order pipeline. Moreover, the use of specialized execution units is minimized. For example, the SIMD integer multiplier and Floating Point divider are used to execute instructions that would normally require a dedicated scalar integer multiplier and integer divider respectively. Finally, other features like activity-based control of instruction issue and dispatch of operations on the Front Side Bus are added for power reduction. This design uses a "sea-of-Functional-Unit-Blocks (FUB)" methodology whereby all cluster hierarchies as well as all unit-level hierarchies are flattened at the chip-level even though the logical partitioning of the chip-level RTL model is comprised of several logical clusters (Floating Point, Integer Execution, Memory Execution, Front-End, Bus Interface, and L2 Cache). This methodology essentially removes all cluster and unit-level hierarchical boundaries resulting in a physical hierarchy where an object-based parallel editing scheme is used for physical design convergence; Fig. 13.1.7 shows the die photo with the logical unit partitions. The physical database consists of 205 unique FUBs (not including repeater stations) and 41K FUB-to-FUB...

Understanding PARSEC performance on contemporary CMPs

“…The Pentium 4 with 20 KB of L1 (12 KB trace cache and 8 KB Dcache) and 512 KB of L2 cache has 55 M transistors [5]. The recently released in-order Intel Atom processor with 32 KB of L1 and 512 KB of L2 has 47 M transistors [8]. While the reduced transistor count is not significant between in-order and OoO, power consumption is considerably lower (as has been the case with other in-order designs from ARM and Sun [15]).…”

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

“…Their processor has a 7 stage pipeline and can issue up to 6 instructions from 6 concurrent threads. A well-known commercial processor that has an in-order SMT architecture is the Intel Atom processor [2] with a two-way in-order pipeline. But none of the mentioned works address hard real-time execution, to our knowledge our project is the first on hard real-time for in-order SMT processors.…”

“…The Intel Atom processor [2] is a famous representative of this class of SMT processors, although it only benefits of a smaller transistor count and lower energy consumption than comparable out-of-order SMT processors. In contrast, this paper addresses the advantage, which is even more important for embedded systems: Because of the deterministic behaviour of superscalar in-order processors, they allow for tight WCET analyses.…”

Architectural core salvaging in a multi-core processor for hard-error tolerance

“…Fortunately, this capability already exists as part of deep-sleep power states such as core C6, which moves state off of a core to an on-die SRAM for power savings [12]. The core C6 array used to store an x86 core's microarchitectural state is about 10KB [8]. Leveraging this capability for architectural core salvaging merely requires adding support (outside the core itself) for migrating the state from one core to another.…”

“…The bandwidth requirements to migrate the architectural state are a few kilobytes in the case of the low-register-count x86 architecture. (Although the core C6 array is 10KB, the array was designed to hold all of the microarchitectural state for a core [8]. We need to store and to migrate only the architectural state.)…”