A sub-1V dual-path noise and distortion canceling CMOS LNA for low power wireless applications

Jafari, Babak Mazhab; Shamsi, Hossein

doi:10.1016/j.mejo.2020.104903

Cited by 4 publications

(1 citation statement)

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“…Methods for eliminating or reduction of LNA noise and also for increasing the voltage gain comprise common source topology 4 and for employing enhanced transconductance method in common gate amplifier. 5 Different noise cancellation techniques 6 are also widely used for the former purpose. Classic strategies for reducing the overall power consumption include current reuse 7,8 and body bias techniques.…”

Section: Introductionmentioning

confidence: 99%

A 0.3–5 GHz, low‐power, area‐efficient, high dynamic range variable gain low‐noise amplifier based on tunable active floating inductor technique

Soleymani

Amiri

Maghami

2021

Circuit Theory & Apps

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An area-efficient low-noise amplifier with extensive voltage gain variation in the frequency range of 0.3 to 5 GHz is proposed. The designed amplifier comprises of two stages of inverter cells, where by utilizing a resistance shunt feedback, the first stage makes the appropriate voltage gain and input impedance matching, and the second stage increases the bandwidth of the circuit utilizing an active floating inductor. Self-forward-body-bias structure is employed in the presented work for reducing power consumption and improving the overall circuit performance. High voltage gain, low power consumption, wide frequency range of operation, lack of physical inductor, and consequently small occupied active area are among the most important features of the proposed circuit. The presented amplifier has been designed and simulated in standard 90-nm and 0.18-μm technologies with 0.9-and 1.2-V supply voltages, respectively, in which important specifications are reported for 90-nm complementary metal-oxide semiconductor (CMOS) process in details. Power consumption of the designed amplifier is 8.8 mW in 90-nm technology with a flat variable voltage gain of À22 to 21.2 dB. The circuit consumes silicon area of 122 Â 112 μm 2 , and in the high-gain mode, the simulated S 11 parameter is less than À10 dB, noise figure is almost 3.2 dB, and the IIP3 is equal to À4 dBm.

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