A study on placement of post silicon clock tuning buffers for mitigating impact of process variation

Abstract

Optical shrink for process migration, manufacturing process variation, temperature and voltage changes lead to clock skew as well as path delay variations in a manufactured chip. Such variations end up degrading the performance of manufactured chips. Since, such variations are hard to predict in pre-silicon phase, tunable clock buffers have been used in several designs. These buffers are tuned to improve maximum operating clock frequency of a design. Previously, we have presented an algorithmic approach that uses delay measurements on a few selected patterns to determine which buffers should be targeted for tuning. In this paper, a study on impact of tunable buffer placement on performance is reported. Greatest benefit from tunable buffer placement is observed, when the clock tree is designed by the proposed tuning system assuming random delay perturbations during design. Accordingly, we present a clock tree synthesis procedure which offer very good protection against process variation as borne out by the results.

Analysis of delay mismatching of digital circuits caused by common environmental fluctuations

“…When in addition to structural differences in logic gates, the number of path elements is increased, the mismatch provoked by environmental conditions fluctuations will be enlarged, because the deviations on propagation time of every single cell is added to the total propagation time as indicated by Eq. (9).…”

“…Process variability, due to its static natures may be partially alleviated by static solutions like layout techniques, introduce corrections steps in the process, etc., but dynamic environmental conditions cannot be treated in the same way because its completely different nature. Techniques to dynamically compensate the effects of process variation [9], [2], temperature [3], voltage and temperature [4], [10] and Process variability-Temperature&Voltage [5] deviations all of them to be used in post-silicon phase and should take into account the mismatch effect shown along this work. …”

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

“…In Ref. [85], the placement of tunable buffers is explored and a considerable yield improvement has been observed.…”

EffiTest

“…After a path in Pt is tested by frequency stepping, its delay has been in a range with a lower bound and an upper bound. For another delay d k that is not measured directly but to be estimated, (4) and (5) are used to calculate the mean value µ k and the standard deviation σ k . According to (4) and (5), σ k is determined exclusively by the covariance matrix, but µ k is affected by dt, which are the delays measured by frequency stepping.…”