A Study of Data Layout in Multi-channel Processing-In-Memory Architecture

Jeong, Taeyang; Choi, Duheon; Han, Sangwoo; Chung, Eui-Young

doi:10.1145/3185089.3185136

Cited by 2 publications

(3 citation statements)

References 9 publications

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“…In big-data processing and embedded applications, the PIM approach can potentially reduce overall memory access latency by placing processing modules near memory and significantly reduce system energy consumption. [36] ReRAM based main memory Speed up: 2360× Six machine learning applications: two CNNs, three multilayer perceptrons (MLPs) and VGG-D --Energy consumption: 895× -Oliveira et al [33] NIM inside 3D stacked memory Simulating capacity: 2× Hodgkin-Huxley model and Izhikevich models Xu et al [97] PIM cores with data prefetcher Speed-up: 44% SPEC CPU 2006 --Off-chip traffic: 16% ---Mis-prefetching predictions: 84% -Jeong et al [98] Multi-channel PIM architecture Speed-up: 393% -Dai et al [99] OVBs on HMC cube Speed-up: 5× Large-scale graph processing…”

Section: Processing-in-memorymentioning

confidence: 99%

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Survey on memory management techniques in heterogeneous computing systems

Hazarika

Poddar

Rahaman

2020

IET Computers & Digital Techniques

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A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high-performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple graphics processing units (GPUs) to accomplish large-scale parallel computing along with CPUs. Data movement between the processor and on-chip or off-chip memory creates a major bottleneck in overall system performance. The CPU/GPU processes all the data on a computer's memory and hence the speed of the data movement to/from memory and the size of the memory affect computer speed. During memory access by any processing element, the memory management unit (MMU) controls the data flow of the computer's main memory and impacts the system performance and power. Change in dynamic random access memory (DRAM) architecture, integration of memory-centric hardware accelerator in the heterogeneous system and Processing-in-Memory (PIM) are the techniques adopted from all the available shared resource management techniques to maximise the system throughput. This survey study presents an analysis of various DRAM designs and their performances. The authors also focus on the architecture, functionality, and performance of different hardware accelerators and PIM systems to reduce memory access time. Some insights and potential directions toward enhancements to existing techniques are also discussed. The requirement of fast, reconfigurable, self-adaptive memory management schemes in the high-speed processing scenario motivates us to track the trend. An effective MMU handles memory protection, cache control and bus arbitration associated with the processors.

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Section: Processing-in-memorymentioning

confidence: 99%

“…Jeong et al [98] proposed a multi‐channel PIM architecture to mitigate the gap between the performance of processor and memory in memory‐intensive applications. This architecture is suitable to communicate data among different PIM modules via several channels.…”

Section: Approaches To Efficient Memory Managementmentioning

confidence: 99%

Survey on memory management techniques in heterogeneous computing systems

Hazarika

Poddar

Rahaman

2020

IET Computers & Digital Techniques

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“…In case we extend the PIMCaffe hardware evaluation platform to multi-channel PIM devices, we can further optimize the PIMCaffe software stack to support more efficient neural network layer mapping schemes. In this regard, Jeong et al proposed studies on the data layout for a multi-channel PIM architecture that has PIM device-todevice communication functionality[36]. A future PIMCaffe system with multi-channel PIM devices can benefit from the multi-channel PIM data layout management methods proposed in the previous work.This article has been accepted for publication in a future issue of this journal, but has not been fully edited.…”

mentioning

confidence: 99%

PIMCaffe: Functional Evaluation of a Machine Learning Framework for In-Memory Neural Processing Unit

et al. 2021

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A large amount of memory usage in recent machine learning applications imposes a high degree of system burden in terms of power and processing speed. To cope with such a problem, Processing-In-Memory (PIM) techniques can be applied to and be an alternative solution. Especially, the recommendation system which is one of the major machine learning applications in data centers requires a huge memory capacity and can be a good candidate application helped by the PIM technique. In this paper, we introduce a machine learning framework designed for in-memory neural processing units and its evaluation environment, named PIMCaffe. PIMCaffe consists of two components; a Caffe2-based deep learning framework that supports PIM acceleration and a PIM-emulating hardware platform. We develop a suite of functions, libraries, application programming interfaces, and a device driver to support the framework. In addition, we implement a prototype Neural Processing Unit (NPU) in PIMCaffe to evaluate the performance of our platform with machine learning applications. Our prototype NPU design includes a vector processor for parallel vector processing and a systolic array unit for matrix multiplication. Using the proposed software framework, we perform a detailed analysis on the in-memory neural processing unit. PIMCaffe supports evaluations of recommendation systems and various convolutional neural network models on the in-memory neural processing unit. PIMCaffe with the NPU shows up to 2.26x, 5.99x, and 1.71x speedup for the recommendation system, AlexNet, and ResNet-50 respectively compared to the ARM Cortex-A53 CPU.

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A Study of Data Layout in Multi-channel Processing-In-Memory Architecture

Cited by 2 publications

References 9 publications

Survey on memory management techniques in heterogeneous computing systems

Survey on memory management techniques in heterogeneous computing systems

PIMCaffe: Functional Evaluation of a Machine Learning Framework for In-Memory Neural Processing Unit

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