A strategy for Grid based t-way test data generation

Younis, Mohammed Issam; Zamli, Kamal Z.; Isa, Nor Ashidi Mat

doi:10.1109/icdfma.2008.4784416

“…It should be noted that the stopping criteria for the test generator is when all inputs are detected (and corresponding outputs are observed). Here, we adopt GMIPOG [10] as our test generator. The results for t=1, 2, 3 are given in Tables 2, 3, 4 respectively.…”

Section: Methodsmentioning

confidence: 99%

“…More recently, there are several strategies that can be generated for high degree interaction (2 ≤ t ≤ 6) ITCH [2], Jenny [3], TConfig [4], TVG [5] IPOG [6] , IPOD [7], IPOF [8] DDA [9]. Finally, GMIPOG [10] is reported as a strategy that supports very high degree of interaction (1 ≤ t ≤ 12).…”

Section: Introductionmentioning

confidence: 97%

Assessing combinatorial interaction strategy for reverse engineering of combinational circuits

Younis

¹

,

Zamli

²

2009

2009 IEEE Symposium on Industrial Electronics &Amp; Applications

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T-way test data generators play an immensely important role for both hardware and software configuration testing. Earlier work concludes that t-way test data generator can achieve 100% coverage without having to regard for more than 6 way interactions. In this paper, we investigate whether or not such a conclusion can be applicable for reverse engineering of combinational circuits. In this case, we reverse engineer a faulty commercial eight segment display controller using our t-way test data generator in order to redesign the replacement unit. We believe that our application of t-way generators for circuit identification is novel. The results demonstrate the need of more than 6 parameter interactions as well as suggest the effectiveness of cumulative test data for reverse engineering applications.

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“…In the last decade, CIT strategies were focused on 2way (pairwise) testing. More recently, several strategies (e.g., Jenny [4], TVG [5], IPOG [6], IPOD [7], IPOF [8], DDA [9], and GMIPOG [10]) that can generate test suite for high degree interaction (2 ≤ t ≤ 6).…”

Section: Introductionmentioning

confidence: 99%

A Strategy for Automatic Quality Signing and Verification Processes for Hardware and Software Testing

Younis

¹

,

Zamli

²

2010

Advances in Software Engineering

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7

0

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We propose a novel strategy to optimize the test suite required for testing both hardware and software in a production line. Here, the strategy is based on two processes: Quality Signing Process and Quality Verification Process, respectively. Unlike earlier work, the proposed strategy is based on integration of black box and white box techniques in order to derive an optimum test suite during the Quality Signing Process. In this case, the generated optimal test suite significantly improves the Quality Verification Process. Considering both processes, the novelty of the proposed strategy is the fact that the optimization and reduction of test suite is performed by selecting only mutant killing test cases from cumulating t-way test cases. As such, the proposed strategy can potentially enhance the quality of product with minimal cost in terms of overall resource usage and time execution. As a case study, this paper describes the step-by-step application of the strategy for testing a 4-bit Magnitude Comparator Integrated Circuits in a production line. Comparatively, our result demonstrates that the proposed strategy outperforms the traditional block partitioning strategy with the mutant score of 100% to 90%, respectively, with the same number of test cases.

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“…Here, there are 80 faults injected in the system. To assist our work, we use GMIPOG [10] to produce the TC 1 FFFFFFFF 53 2 FFFFFTTF 55 3 FFFFTTTT 55 4 TFTTFFFF 59 5 TFFTFTTT 61 6 TFTFTTTT 61 7 TTTTFFFF 61 8 TTTTTFFF 64 9 TTTTTTTT 72 in a cumulative mode. Following the steps in TQS process, Table 2 demonstrates the derivation of OTS.…”

Section: Case Studymentioning

confidence: 99%

“…More recently, several strategies (e.g., Jenny [4], TVG [5], IPOG [6], IPOD [7], IPOF [8], DDA [9], and GMIPOG [10]) that can generate test suite for high degree interaction (2 ≤ t ≤ 6).…”

Section: Introductionmentioning

confidence: 99%

A Strategy for Automatic Quality Signing and Verification Processes for Hardware and Software Testing

2016

Data Structure and Software Engineering

0

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We propose a novel strategy to optimize the test suite required for testing both hardware and software in a production line. Here, the strategy is based on two processes: Quality Signing Process and Quality Verification Process, respectively. Unlike earlier work, the proposed strategy is based on integration of black box and white box techniques in order to derive an optimum test suite during the Quality Signing Process. In this case, the generated optimal test suite significantly improves the Quality Verification Process. Considering both processes, the novelty of the proposed strategy is the fact that the optimization and reduction of test suite is performed by selecting only mutant killing test cases from cumulating t-way test cases. As such, the proposed strategy can potentially enhance the quality of product with minimal cost in terms of overall resource usage and time execution. As a case study, this paper describes the step-by-step application of the strategy for testing a 4-bit Magnitude Comparator Integrated Circuits in a production line. Comparatively, our result demonstrates that the proposed strategy outperforms the traditional block partitioning strategy with the mutant score of 100% to 90%, respectively, with the same number of test cases.

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A strategy for Grid based t-way test data generation

Cited by 22 publications

References 2 publications

Assessing combinatorial interaction strategy for reverse engineering of combinational circuits

Assessing combinatorial interaction strategy for reverse engineering of combinational circuits

A Strategy for Automatic Quality Signing and Verification Processes for Hardware and Software Testing

A Strategy for Automatic Quality Signing and Verification Processes for Hardware and Software Testing

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