A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test

SUMMARYIn at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the response for a test vector is captured by flip-flops results in excessive voltage drops, known as IR-drops, which may cause significant capture-induced yield loss. In low capture power test generation, the test vectors that violate capture power constraints in an initial test set are defined as capture-unsafe test vectors, while faults that are detected solely by capture-unsafe test vectors are defined as unsafe faults. It is necessary to regenerate the test vectors used to detect unsafe faults in order to prevent unnecessary yield losses. In this paper, we propose a new low capture power test generation method based on fault simulation that uses capture-safe test vectors in an initial test set. Experimental results show that the use of this method reduces the number of unsafe faults by 94% while requiring just 18% more additional test vectors on average, and while requiring less test generation time compared with the conventional low capture power test generation method.

“…To estimate LSA, several metrics have been proposed [20], [22]. Most previous studies use simple metrics due to the need for computation efficiency.…”

Section: Capture Power Problemmentioning

confidence: 99%

A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation

Hosokawa

Hirai

Yamauchi

et al. 2017

“…(S1) Global: The switching activity of the entire circuit is checked to determine capture safety [8]- [11]. Since capture malfunction is a local phenomenon that usually occurs at the endpoint of a sensitized long path, the global metric may not be able to provide an accurate determination [8].…”

Section: Previous Metricsmentioning

confidence: 99%

“…Since capture malfunction is a local phenomenon that usually occurs at the endpoint of a sensitized long path, the global metric may not be able to provide an accurate determination [8].…”

Section: Previous Metricsmentioning

confidence: 99%

“…2. From the spatial perspective, capturesafety checking metrics can be classified as (S1) global (the switching activity of the entire circuit is checked) [9]- [11], (S2) regional (the switching activity in specific regions is checked) [8], (S3) structural-long-path-based (the switching activity around structurally long paths is checked) [12], and (S4) sensitized-long-path-based (the switching activity around sensitized long paths is checked) [13]. From the temporal perspective, capture-safety checking metrics can be classified as (T1) total (the switching activity for the whole launch cycle is checked) [9]- [11], (T2) instantaneous (peak or instantaneous switching activity is checked) [8], and (T3) transition-window-based (switching activity in the transition window is checked) [14].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing

Miyase

Sakai

Wen

et al. 2013

SUMMARYTest power has become a critical issue, especially for lowpower devices with deeply optimized functional power profiles. Particularly, excessive capture power in at-speed scan testing may cause timing failures that result in test-induced yield loss. This has made capturesafety checking mandatory for test vectors. However, previous capturesafety checking metrics suffer from inadequate accuracy since they ignore the time relations among different transitions caused by a test vector in a circuit. This paper presents a novel metric called the Transition-TimeRelation-based (TTR) metric which takes transition time relations into consideration in capture-safety checking. Detailed analysis done on an industrial circuit has demonstrated the advantages of the TTR metric. Capturesafety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation.

“…A 10% drop in power supply voltage has been shown to be capable of increasing path delay by 30% [5]. Obviously, this may result in capture failures at C 2 [4], thus leading to test-induced yield loss [6]- [8]. This problem is worsening rapidly amongst deep-submicron and low-power chips [6].…”

Section: Introductionmentioning

confidence: 99%

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

Miyase

Wen

Furukawa

et al. 2010

SUMMARYAt-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-GatingBased Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (ClockDisabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.