A Steep Slope MBE-Grown Thin p-Ge Channel FETs on Bulk Ge<sub>-on-</sub>Si Using HZO Internal Voltage Amplification

Choudhary, Sumit; Schwarz, Daniel; Funk, Hannes S.; Weißhaupt, David; Khosla, Robin; Sharma, Satinder K.; Schulze, Jörg

doi:10.1109/ted.2022.3161857

Cited by 12 publications

(5 citation statements)

References 33 publications

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“…Figure 11(f) demonstrates the effect of temperature on the CP 1-dB of the Ti/HfO 2 /Al 2 O 3 /Ge CP-DGTFET device structure in the presence of ±10 12 cm −2 ITC. The maximum CP 1-dB decreases from ∼30.55 dBm to ∼28.36 dBm with variation in temperature from 275 K to 375 K at a fixed PITC of +10 12 cm −2 due to the CP 1-dB dependency on transconductance as per equation (17).…”

Section: Resultsmentioning

confidence: 99%

“…Numerous strategies have been adopted to resolve the aforementioned concerns of TFETs, such as integration of high-mobility lowenergy bandgap materials (e.g. : SiGe, Ge, GeSn), doping engineering [6,7], nanowires [8], gate engineering [9], III-V & heterojunction TFET [10,11], charge plasma (CP) and doping-less TFET [12][13][14], pocket doping [15], and so on [16][17][18][19][20]. Among these, pocket doping, which involves the integration of the physical pocket region, is expected to result in superior TFET performance, but at the cost of additional process steps, such as extra doping, which increases manufacturing complexity and cost.…”

Section: Introductionmentioning

confidence: 99%

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Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO₂/Al₂O₃/Ge, double gate TFET

Yadav,

Chappa,

Baghel

et al. 2024

Eng. Res. Express

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The Tunnel Field Effect Transistor (TFET) often suffers from low ON current (ION), charge traps, and thermal variability, which limits its performance and reliability. To address these issues, the source work function engineered Ge Charge Plasma Double Gate Tunnel Field Effect Transistor (CP-DGTFET) device structure with HfO2/Al2O3 bilayer gate dielectric is designed and investigated using numerical TCAD simulations. The proposed Ti/HfO2/Al2O3/Ge CP-DGTFET device structure showed excellent DC characteristics with exceptional ION, ION/IOFF ratio, and minimal sub-threshold swing (S) of ~3.04×10-4 A/µm, ~1.2×1010, and ~3.4 mV/dec, respectively. Furthermore, the device’s analog characteristics displayed good transconductance, cut-off frequency, and gain bandwidth product of ~0.75 mS/µm, ~0.97 THz, and ~0.10 THz, respectively. Moreover, the charge trap exploration divulges that positive ITCs can enhance device performance, whereas negative ITCs can adversely impact the electrical characteristics of CP-DGTFET. Additionally, the temperature-dependent analysis showed that the OFF-state leakage current increases from ~1.7×10-15 A/µm to 2.4×10-10 A/µm with temperature fluctuations from 275 K to 375 K. Overall, the work function-engineered CP-based Ti/HfO2/Al2O3/Ge DGTFET device structure shows great potential for improving the performance and reliability of Ge TFET technology.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO₂/Al₂O₃/Ge, double gate TFET

Yadav,

Chappa,

Baghel

et al. 2024

Eng. Res. Express

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“…Besides, the NC effect also proves to be compatible with all kinds of semiconductor channel materials, from 3D Si, Ge, 2D (transition metal dichalcogenides) TMDCs such as MoS2, WSe2, black phosphorus to 1D carbon nanotube. Prospective results have been achieved both theoretically and experimentally [74][75][76][77][78]. But one exception exists: there hasn't been an experiment that has achieved sub-60 mV/dec SS in NC-FETs based on Ⅲ-Ⅴ group semiconductors until now due to the serious interface states between ferroelectric materials and Ⅲ-Ⅴ semiconductor layers.…”

Section: ) Nc-fet Device Typementioning

confidence: 99%

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Qin

Wei

et al. 2023

IEEE Access

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With transistors scaling down to 3 nm node and beyond, short channel effect (SCE) as well as power consumption dissipation present immense challenges for further scaling down of the transistor. Hence the Gate all around field effect transistor (GAA-FET) is proposed to replace the Fin field effect transistor (FinFET) in 3 nm technology node and beyond due to its better gate control over the channel with surrounding gate structure, thus providing improved SCE constraint ability. Traditional transistors suffer from the problems of "Boltzmann Tyranny" and cannot overcome the subthreshold swing (SS) limit of 60 mV/dec at room temperature. To maintain high Ion and avoid Ioff from increasing too much, supply voltage (VDD) of the conventional transistor cannot scale down proportionally with the dimension of the transistor. The concept of negative capacitance (NC) has been demonstrated to be able to obtain sub-60 mV/dec SS with the ability of amplifying the potential of the channel region without VDD increment. The novel device structure of negative capacitance gate all around field effect transistor ( NC GAA-FET) can combine both the advantages of GAA-FET and NC-FET, and is the most promising ultra-low power consumption device and promises to sustain the Moore's law further beyond what is predicted now. Whereas, according to our knowledge, there have been few review papers about NC GAA-FET till now. Herein, we summarize the recent advances of the NC GAA-FET both in simulation and experimental aspects, which we believe will bring about profound changes to the further development of NC GAA-FET devices.INDEX TERMS Negative capacitance effect, short channel effect, subthreshold swing, power consumption dissipation, negative capacitance gate all around field effect transistor.

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“…In this regard, low-temperature molecular beam epitaxy (MBE) of thin, flat and defect-free Ge layers on a SOI platform proved to be a viable alternative leveraging the advantages of Ge, bypassing GeOI processing issues and providing a low-cost alternative to GeOI platforms. [11] II. DEVICE FABRICATION In this work, we report on Ge based RFETs implemented on a SOI platform with high and symmetric on-state conductance for both, n-and p-type operation (see Figure 1a).…”

Section: Introductionmentioning

confidence: 99%

A Run-Time Reconfigurable Ge Field-Effect Transistor With Symmetric On-States

Fuchsberger,

Wind,

Nazzari

et al. 2024

IEEE J. Electron Devices Soc.

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Here, we present a Ge based reconfigurable transistor, capable of dynamic run-time switching between n-and p-type operation with enhanced performance compared to state-of-theart Si devices. Thereto, we have monolithically integrated an ultra-thin epitaxial and defect-free Ge layer on a Si on insulator platform. To evade the commonly observed process variability of Ni-germanides, Al-Si-Ge multi-heterojunction contacts have been employed, providing process stability and the required equal injection capabilities for electrons and holes. Integration into a three top-gate transistor enables effective polarity control and efficient leakage current suppression to limit static power dissipation. Exploiting the advantages of multi-gate transistors, combinational wired-AND gates are shown to be capable of extending a single transistor to a logic gate. Notably, the obtained Al-Si-Ge multi-heterojunction reconfigurable transistors constitute the first CMOS compatible platform to combine efficient polarity control enabling the envisioned performance enhancements of Ge based reconfigurable transistors.

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A Steep Slope MBE-Grown Thin p-Ge Channel FETs on Bulk Ge_-on-Si Using HZO Internal Voltage Amplification

Cited by 12 publications

References 33 publications

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO₂/Al₂O₃/Ge, double gate TFET

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO₂/Al₂O₃/Ge, double gate TFET

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

A Run-Time Reconfigurable Ge Field-Effect Transistor With Symmetric On-States

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A Steep Slope MBE-Grown Thin p-Ge Channel FETs on Bulk Ge-on-Si Using HZO Internal Voltage Amplification

Cited by 12 publications

References 33 publications

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO2/Al2O3/Ge, double gate TFET

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO2/Al2O3/Ge, double gate TFET

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

A Run-Time Reconfigurable Ge Field-Effect Transistor With Symmetric On-States

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Product

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A Steep Slope MBE-Grown Thin p-Ge Channel FETs on Bulk Ge_-on-Si Using HZO Internal Voltage Amplification

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO₂/Al₂O₃/Ge, double gate TFET

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO₂/Al₂O₃/Ge, double gate TFET