A Statistical Analysis of the Number of Failing Chips Distribution

O'Donoghue, G.; Gomez-Uribe, Carlos Alberto

doi:10.1109/tsm.2008.2001208

Cited by 8 publications

(2 citation statements)

References 13 publications

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“…In our experimental data, it is observed that chips near the edge of the wafer had a higher rate of failure than chips at the center. This is consistent with the Edge Effect observed in [9] and [10]. Because of different error distributions at the center and circumference of the wafer, it is difficult to fit a single distribution over the whole wafer.…”

Section: Chip Distributionsupporting

confidence: 85%

“…Then the error is divided among the chips which are placed on the wafer. A bimodal distribution which takes into account the Edge Effect [10] is used for radial error distribution of chips on the wafer. Before injecting different chip errors, specific errors are also injected into the wafer which bring in some anomalies in the distribution data.…”

Section: Fig 16 Working Of the Defect Injectormentioning

confidence: 99%

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A Statistical Wafer Scale Error and Redundancy Analysis Simulator

Atishay¹,

Gupta²,

Sonawat³

et al. 2020

IFIP Advances in Information and Communication Technology

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Manufacturing a DRAM chip involves multiple steps. External impurities, faulty deposition, or manufacturing errors in any of these steps could generate chips with faulty memory cells, rendering the chip unusable. To overcome these faulty memory cells, redundancies are included in the memory, allowing mapping of faulty memory cells to these redundant cells. The process of mapping faulty cells to redundant cells is called Redundancy Analysis (RA). Different RA algorithms have been developed and are often tested on randomly generated defect to test their efficiency and execution time. But we observed that, the defect pattern of a chip is not completely random, it follows a distribution pattern and the algorithms should be tested on chips with similar error distribution patterns. So, in this paper, we propose a Statistical Wafer Scale Error and Redundancy Analysis Simulator to generate defects on the chips similar to defects on the manufacturing line. The simulated errors on the chips are based on statistical models derived from real data. After generating defects on the chip, execution, comparison and benchmarking of algorithms based on yield and execution time is done. The simulator gives insights on algorithm behavior with different kinds of memory architectures and defect patterns. This allows designers of memory architecture and RA algorithm to simulate, predict and improve the wafer yield for different RA algorithm designs and memory architectures before manufacturing a new memory device.

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Section: Chip Distributionsupporting

confidence: 85%

Section: Fig 16 Working Of the Defect Injectormentioning

confidence: 99%