A spur free 0.4-V 88-μW 200-MHz phase-locked loop

Abstract

An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm 2 and consumes 88 W at 0.4-V supply for 200-MHz operation.