A Specialized BTB Organization for Servers

Asheim, Truls; Grot, Boris; Kumar, Rakesh

doi:10.1145/3559009.3569692

Cited by 2 publications

(2 citation statements)

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“…As program sizes continue to grow, the demand for larger BTB capacities is increasing. To strike a balance between performance and power consumption, researchers have explored various BTB architecture designs [23][24][25]. However, as directional predictors become more complex, the BTB needs to provide addresses for prediction and prefetching.…”

Section: The Two-level Btb Structurementioning

confidence: 99%

Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism

Nian,

Liu,

Gao

et al. 2024

Electronics

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Modern processors often face challenges when handling instructions that overwhelm the branch target buffer (BTB), leading to front-end bottlenecks. As the BTB’s capacity increases, its prediction module can become slower and power-hungry. In this paper, we introduce a straightforward yet highly effective two-level prediction mechanism to mitigate the escalating power consumption in the BTB structure, achieved by reducing the number of accesses. Our approach incorporates two main elements: M-BTB and V-BTB. M-BTB encompasses the first-level prediction mechanism and a fully associative BTB, while V-BTB houses the second-level prediction mechanism and a set-associative BTB. To implement our prediction mechanism, we optimize the traditional two-level BTB structure. The first level employs the skew mechanism, and the second level dissects the tag bits to create the Partial tag. These two levels of prediction mechanism correspond to the bank/way prediction for the two-level BTB structure. Our experimental results show that the first-stage prediction mechanism reduces M-BTB accesses by 75%, while the second-stage prediction mechanism ensures that over 98% of addresses require just zero or one way of the V-BTB to achieve a hit result. Our proposed approach achieves a remarkable 86–97% reduction in power consumption, with a minimal impact on performance and an increase in overall area efficiency.

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Section: The Two-level Btb Structurementioning

confidence: 99%

Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism

Nian,

Liu,

Gao

et al. 2024

Electronics

View full text Add to dashboard Cite

show abstract

“…Prior work [10], [11], [23], [47]- [49] has also explored mechanisms to reduce the storage cost of branch targets. Seznec [47], [48] proposed to break the target address into page number and offset; and store a pointer to the page number, along with the page offset, in the BTB while the page number itself is stored in a separate structure.…”

Section: G Analyzing Target Offset Distribution In More Workloadsmentioning

confidence: 99%

A Storage-Effective BTB Organization for Servers

Asheim

Grot

Kumar

2023

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

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Many contemporary applications feature multimegabyte instruction footprints that overwhelm the capacity of branch target buffers (BTB) and instruction caches (L1-I), causing frequent front-end stalls that inevitably hurt performance. BTB capacity is crucial for performance as a sufficiently large BTB enables the front-end to accurately resolve the upcoming execution path and steer instruction fetch appropriately. Moreover, it also enables highly effective fetch-directed instruction prefetching that can eliminate a large portion L1-I misses. For these reasons, commercial processors allocate vast amounts of storage capacity to BTBs.This work aims to reduce BTB storage requirements by optimizing the organization of BTB entries. Our key insight is that storing branch target offsets, instead of full or compressed targets, can drastically reduce BTB storage cost as the vast majority of dynamic branches have short offsets requiring just a handful of bits to encode. Based on this insight, we size the ways of a set associative BTB to hold different number of target offset bits such that each way stores offsets within a particular range. Doing so enables a dramatic reduction in storage for target addresses. Our final design, called BTB-X, uses an 8-way set associative BTB with differently sized ways that enables it to track about 2.24x more branches than a conventional BTB and 1.3x more branches than a storage-optimized state-of-the-art BTB organization, called PDede, with the same storage budget.

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A Specialized BTB Organization for Servers

Cited by 2 publications

References 1 publication

Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism

Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism

A Storage-Effective BTB Organization for Servers

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