A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS

Gopal, Srinivasan; Agarwal, Pawan; Baylon, Joe; Renaud, Luke; Ali, Sheikh Nijam; Pande, Partha Pratim; Heo, Deukhyoun

doi:10.1109/jetcas.2018.2852624

Cited by 12 publications

(4 citation statements)

References 28 publications

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“…Our energy metric is at 130nm, and the lowest state-of-art metric at 65nm. Assuming that the energy scales by L 2 , the scaled energy consumption approaches that of the state-of-art 2) In [23], linearity of the delay-cell is based on backbody biasing, which, is theoretically non-linear. In the proposed cell, the output-input characteristics are linear, due to the linear voltage-initialization step 3) Despite noise limitations, the number of bits that can be accommodated in the mixed-signal multiplier is higher than state-of-art.…”

Section: Multiplier Simulationmentioning

confidence: 99%

“…Within the purview of time-based accumulation, pulsewidth [20], [21] and pulse-delay [18], [22], [23] are the two modulation schemes that have been demonstrated onchip. Of these, pulse-(or, event) delay is more promising for MAC applications due to (1) free addition/subtraction in case of delay, and (2) requirement of peripheral pulse re-routing circuitry requirements in the prior.…”

Section: Introductionmentioning

confidence: 99%

“…Delay-modulation via programming voltages, for both − low-power front-end analog processing and approximatecomputing acceleration, was demonstrated in [23]. Applying a small-signal analog input to the back-gate of the transistor modulated the threshold voltage and hence, the delay.…”

Section: Introductionmentioning

confidence: 99%

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Linear Delay-cell Design for Low-energy Delay Multiplication and Accumulation

Shukla¹

2020

Preprint

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A practical deep neural network's (DNN) evaluation involves thousands of multiply-and-accumulate (MAC) operations. To extend DNN's superior inference capabilities to energy constrained devices, architectures and circuits that minimize energy-per-MAC must be developed. In this respect, analog delay-based MAC is advantageous due to reasons both extrinsic and intrinsic to the MAC implementation − (1) lower fixedpoint precision requirement for a DNN's evaluation, (2) better dynamic range than charge-based accumulation, for smaller technology nodes, and (3) simpler analog-digital interfacing. Implementing DNNs using delay-based MAC requires mixedsignal delay multipliers that accept digitally stored weights and analog voltages as arguments. To this end, a novel, linearly tune-able delay-cell is proposed, wherein, the delay is realized using an inverted MOS capacitor's (C * ) steady discharge from a linearly input-voltage dependent initial charge. The cell is analytically modeled, constraints for its functional validity are determined, and jitter-models are developed. Multiple cells with scaled delays, corresponding to each bit of the digital argument, must be cascaded to form the multiplier. To realize such bitwise delay-scaling of the cells, a biasing circuit is proposed that generates sub-threshold gate-voltages to scale C * 's discharging rate, and thus area-expensive transistor width-scaling is avoided. For 130nm CMOS technology, the theoretical constraints and limits on jitter are used to find the optimal design-point and quantify the jitter versus bits-per-multiplier trade-off. Schematiclevel simulations show a worst-case energy-consumption close to the state-of-art, and thus, feasibility of the cell.

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Section: Multiplier Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Linear Delay-cell Design for Low-energy Delay Multiplication and Accumulation

Shukla¹

2020

Preprint

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“…Moreover, another drawback is the excessively large increase in delay when the supply voltage (or the gate-source voltage of the current-starved transistor) becomes excessively low. Another approach [9] is based on the modulation of the transistor threshold voltage and hence, the delay is obtained by applying a small-signal analog input to the back-gate, but this solution also presents a nonlinear transcharacteristic because the threshold voltage varies with the input in a square-root fashion, and hence the delay is nonlinear. Another issue in practically all electronic circuits is the susceptibility to electromagnetic interferences (EMI).…”

Section: Introductionmentioning

confidence: 99%

Increasing EMI Immunity and Linearity of a CMOS 180 nm Voltage-to-Delay Converter

2022

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This paper presents a voltage-controlled delay unit (VCDU) with a novel architecture allowing for a wide input range of linearity and an improved immunity to electromagnetic interferences. The circuit is based on a current-starved inverter with a biasing technique to extend the input voltage range of linearity near to the rail-to-rail linearity range. The proposed scheme was designed by UMC 180 nm standard CMOS process and works without power-hungry amplifiers or comparators. It has a voltage supply of 1.8 V and exhibits a rail-to-rail linearity range (0–1.8 V) with an average EMI-induced jitter of only 1% of the nominal delay.

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