A SoPC FPGA Implementing of an Enhanced Parallel CFAR Architecture

Msadaa, Sadok; Lahbib, Younes; Mami, Abdelkader

doi:10.1109/setit54465.2022.9875739

Cited by 3 publications

(3 citation statements)

References 11 publications

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“…Table 4 shows a comparison of the results between the proposed method and other CFAR processors in [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 ]. For a fair comparison, we compared the speed performance in terms of the normalized operation time,

, which was calculated based on FPGA process technology [ 32 ].…”

Section: Hardware Architecturementioning

confidence: 99%

“…An ACOSD CFAR-based algorithm was implemented in [ 22 , 23 , 24 , 25 ] for the case where the background distribution is log-normal. The CFAR processors in [ 22 , 25 ] have low complexity and fast operation time but cannot be applied to various environments, and a proposed method [ 23 ] has a problem with slow operation time. The CFAR processor presented in [ 24 ] has a fast operation time but has high hardware complexity in supporting various algorithms.…”

Section: Hardware Architecturementioning

confidence: 99%

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FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

Sim

Heo

Jung

et al. 2023

Sensors

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The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 μs to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation.

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, which was calculated based on FPGA process technology [ 32 ].…”

Section: Hardware Architecturementioning

confidence: 99%

Section: Hardware Architecturementioning

confidence: 99%

FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

Sim

Heo

Jung

et al. 2023

Sensors

View full text Add to dashboard Cite

show abstract

“…A highly parametrizable and configurable implementation is reported in [88], which features 7 different CFAR algorithms and guarantees real time performances. Other noticeable hardware implementations of the CFAR algorithm are discussed in [89][90][91].…”

Section: Digital Hardware Architectures For On-vehicle Sensing Tasksmentioning

confidence: 99%

A Survey of Automotive Radar and Lidar Signal Processing and Architectures

Giuffrida,

Masera,

Martina

2023

Chips

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In recent years, the development of Advanced Driver-Assistance Systems (ADASs) is driving the need for more reliable and precise on-vehicle sensing. Radar and lidar are crucial in this framework, since they allow sensing of vehicle’s surroundings. In such a scenario, it is necessary to master these sensing systems, and knowing their similarities and differences is important. Due to ADAS’s intrinsic real-time performance requirements, it is almost mandatory to be aware of the processing algorithms required by radar and lidar to understand what can be optimized and what actions can be taken to approach the real-time requirement. This review aims to present state-of-the-art radar and lidar technology, mainly focusing on modulation schemes and imaging systems, highlighting their weaknesses and strengths. Then, an overview of the sensor data processing algorithms is provided, with some considerations on what type of algorithms can be accelerated in hardware, pointing to some implementations from the literature. In conclusion, the basic concepts of sensor fusion are presented, and a comparison between radar and lidar is performed.

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An improved CFAR algorithm for multiple environmental conditions

Rihan,

Nossair,

Mubarak

2024

SIViP

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The primary objective of radar digital signal processing is to detect and identify targets in complicated situations, such as those involving clutter or several closely positioned targets. The constant false alarm rate (CFAR) method is more effective for target recognition and has better control over the false alarm rate. Many studies have been conducted on the design of CFAR, but previous CFAR algorithms have not been effective in all or most environmental fields and target scenarios. In this study, an algorithm called Censored Mean Clutter Map CFAR (CM-CM CFAR) has been developed and tested for various environmental conditions. When compared to a fixed false alarm rate, the suggested CFAR algorithm’s Monte Carlo simulation results demonstrated a high detection probability in a variety of environments. This work designs a real-time CM-CM CFAR processor using field-programmable gate array (FPGA) technologies. Xilinx ARTIX 7 FPGA technology is used to develop and map a scalable parallel framework. Consequently, the implementation required 23,741 LUTs and 1825 FF. It is verified that the complexity and operating speed of the suggested CFAR processor are extremely appropriate for real-time implementation when compared to the results of the previously proposed FPGA implementation.

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A SoPC FPGA Implementing of an Enhanced Parallel CFAR Architecture

Cited by 3 publications

References 11 publications

FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

A Survey of Automotive Radar and Lidar Signal Processing and Architectures

An improved CFAR algorithm for multiple environmental conditions

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