A Solution to VLSI: Digital Circuits Design in Quantum Dot Cellular Automata Technology

Abstract

Quantum Dot Cellular Automata is a Nano device efficient than other devices in nanotechnology for the last two decades. It is beneficial over Complementary Metal Oxide Semiconductor technology like high speed, low energy dissipation, high device density and high computation efficiency. To achieve further optimization different methods like simplifications in Boolean expressions, tile method, clocking scheme, cell placement, cell arrangement, novel input techniques, etc., are in use. These methods improve the performance metrics in terms of QCA Cells, total circuit area, delay in output, power consumption, and coplanar or multilayer layout. This paper is about the novel NOT gate layout designed with efficient parameters compared to existing NOT gates except area parameters with analysis and XOR gate and multiplexer circuits. The novel gate provides an improvement of 55% in the number of cells, polarization raised by 0.33, and an 80.77% improvement in total area. These circuits illustrate further scope in QCA circuit design efficiently. XOR circuit shows area reduction up to 0.006 μm2 with 0.5 clock cycle delay. Further optimization in XOR parameters and with this novel NOT gate researchers can optimize parameters to bring revolution and digitalization.