A software/reconfigurable hardware SAT solver

Abstract

Abstract-This paper introduces a novel approach for solving the Boolean satisfiability (SAT) problem by combining software and configurable hardware. The suggested technique avoids instance-specific hardware compilation and, as a result, allows the total problem solving time to be reduced compared to other approaches that have been proposed. Moreover, the technique permits problems that exceed the resources of the available reconfigurable hardware to be solved. The paper presents the results obtained with some of the DIMACS benchmarks and a comparison of our implementation with other available SAT solvers based on reconfigurable hardware. The hardware part of the satisfier was realized on Virtex XCV812E FPGA, which has a large volume of embedded memory blocks that provide direct support for the proposed approach.Index Terms-Boolean satisfiability, configurable computing, field-programmable gate array (FPGA), partitioning.

Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers

“…It is known that the SAT problem can be formulated over different models [3] and we will consider for such purposes ternary matrices [4,5]. They have been chosen because of the reasons reported in [4,5].…”

“…• Matrix compression and decompression have been employed for the hardware/software SAT solver considered in [5].…”

“…In accordance with [5] a matrix-oriented SAT solver executes operations over rows/columns of a ternary matrix applying the following set of rules:…”

“…2. On the one hand the majority of the involved operations are similar to [5]. On the other hand the algorithm has a number of distinctive features which make possible the required hardware resources to be reduced without a degradation of performance.…”

“…All the other operations are exactly the same as in [5] and we will not replicate them to keep the description short. Note that any compression technique leads to non-equal sizes of different rows (vectors) and this conducts to irregularity of different SAT solver blocks, such as the matrix memory, the combinational circuit, etc.…”