A software/hardware co-debug platform for multi-core systems

Lee, Kuen-Jong; Su, Alan P.; Chen, Long-Feng; Jhou, Jia-Wei; Kuo, Jiff; Liu, Mark

doi:10.1109/asicon.2011.6157171

Cited by 5 publications

(5 citation statements)

References 6 publications

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“…These mechanisms are designed for multicore processors; hence, they are able to send stop signals to other processors and act on a whole system. These features are used by development environments, and software‐hardware co‐debug platforms have been proposed …”

Section: Discussion and Related Workmentioning

confidence: 99%

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Hardware‐assisted software event tracing

Verge

Ezzati‐Jivan

Dagenais

2017

Concurrency and Computation

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Summary Event tracing is a reliable and a low‐intrusiveness method to debug and optimize systems and processes. Low overhead is particularly important in embedded systems where resources and energy consumption is critical. The most advanced tracing infrastructures achieve a very low footprint on the traced software, bringing each tracepoint overhead to less than a microsecond. To reduce this still non‐negligible impact, the use of dedicated hardware resources is promising. In this paper, we propose complementary methods for tracing that rely on hardware modules to assist software tracing. We designed solutions to take advantage of CoreSight STM, CoreSight ETM, and Intel BTS, which are present on most newer ARM‐based systems‐on‐chip and Intel x86 processors. Our results show that the time overhead for tracing can be reduced by up to 10 times when assisted by hardware, as compared to software tracing with LTTng, a high‐performance tracer for Linux. We also propose a modification to the Perf tool to speed BTS execution tracing up to 65%.

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Section: Discussion and Related Workmentioning

confidence: 99%

“…These features are used by development environments, 30,31 and software-hardware co-debug platforms have been proposed. 32,33…”

Section: Debuggingmentioning

confidence: 99%

Hardware‐assisted software event tracing

Verge

Ezzati‐Jivan

Dagenais

2017

Concurrency and Computation

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“…In the following, some related debugging methods and background knowledge which is essential would be described in Chapter 2. Our SW/HW To solve the problems, they have made some modifications to the platform to support hardware breakpoint setting and designed Design Automation System for SoC Test Platform (DASTEP), which is a graphical user interface (GUI) makes hardware debugging more friendly [9,10]. They have also made use of Embedded Trace Macrocell (ETM) [11] and RealView Development Suite (RVDS) [12] which are designed by ARM Inc. to support software debugging.…”

Section: Organization Of the Thesismentioning

confidence: 99%

A unified GDB-based source-transaction level SW/HW co-debugging

Chang

Hou

Huang

2016

2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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In most traditional System-on-Chip (SoC) debugging method, software debugging is performed at the source/instruction-level while the hardware is debugged at the cycle-level. To make SoC debugging more efficient, this thesis presents a unified co-debugging method with the primary goal of bridging the abstraction gap between software debugging and hardware debugging. With the help of the proposed retargetable socket-based in circuit emulator (SBICE), the transaction of any socket-compliant intellectual property core (IP-core) on the system interconnect could be halted, monitored or even modified. The GNU Debugger (GDB) and Open On-Chip Debugger (OpenOCD) are also enhanced to provide a unified interface for integrated manipulation of SBICE and the on-chip CPU's ICE. On this interface, a system developer could monitor/debug the system software and the interacting IP-cores in a consistent way. This makes the process of system bug identification more efficient and time-to-market could be reduced substantially.

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“…Due to the limitations of the data transmission bandwidth and the memory space, the trace-based approach usually can only focus on a small part of a SoC and record the data in a short interval, and often requires some data compression schemes [3][4]. The Run-stop debug approach [8][9][10][11][12] allows the user to set a breakpoint, run the system, and stop the system at the breakpoint. Once stopped, the internal state of the system can be delivered to external devices such as a PC for observation.…”

Section: Introductionmentioning

confidence: 99%

“…Once stopped, the internal state of the system can be delivered to external devices such as a PC for observation. In some debug schemes [11][12], the system can be resumed to its normal function and continue the debug operations, which include setting a new breakpoint, executing a single-step operation, stopping at a new breakpoint, and observing the new states. Such a run-stop-resume debug methodology is similar to what a software debugger provides.…”

Section: Introductionmentioning

confidence: 99%