A Software Defined Radio Transceiver Based on Dynamic Partial Reconfiguration

Hosny, Sherif; Elnader, Eslam; Gamal, Mostafa; Hussien, Abdelrhman; Khalil, A. H.; Mostafa, Hassan

doi:10.1109/ngcas.2018.8572253

Cited by 9 publications

(3 citation statements)

References 8 publications

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“…For instance, researchers in [24] discuss their approach to an SDR design, based on the Analog Devices FMCOMMS3, ZedBoard / ZC706, and MathWorks and Xilinx software tools. Other studies have investigated the potential of dynamic partial reconfiguration techniques for implementing flexible SDRs [25].…”

Section: Literature Reviewmentioning

confidence: 99%

Control and Visualisation of a Software Defined Radio System on the Xilinx RFSoC Platform Using the PYNQ Framework

et al. 2020

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The availability of commercial Radio Frequency System on Chip (RFSoC) devices brings new possibilities for implementing Software Defined Radio (SDR) systems. Such systems are of increasing interest given the pace of innovation in wireless technology, and the pressure on RF spectrum resources, leading to a growing need to access the spectrum in more dynamic and innovative ways. In this paper, we present an SDR demonstration system based on the Xilinx RFSoC platform, which leverages the Pythonbased 'PYNQ' (Python Productivity for Zynq) software framework. In doing so, we highlight features that can be extremely useful for prototyping radio system design. Notably, our developed system features Python-based control of hardware processing blocks and Radio Frequency (RF) data converters, as well as direct visualisation of communications signals captured within the chip. The system architecture is reviewed, hardware and software components are discussed, functionality is demonstrated, and aspects of the system's performance are evaluated. Finally, it is noted that this combined RFSoC + PYNQ approach is readily extensible for other SDR systems; we highlight our online shared resources, and invite other engineers to investigate and build upon our work.

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Section: Literature Reviewmentioning

confidence: 99%

Control and Visualisation of a Software Defined Radio System on the Xilinx RFSoC Platform Using the PYNQ Framework

et al. 2020

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“…Dynamic reconfiguration and Dynamic Partial Reconfiguration (DPR) is rapidly growing in popularity as it enables FPGA designs to be changed at run-time to better meet changing systems demands [25,11]. The use of DPR is rapidly gaining popularity over a number of sectors including: fault recovery [5], memory controllers [36], real-time signal processing [12], software defined radio [35,18,17], cognitive radio [39], bandwidth reduction [30], video filters [20], and RADAR signal processing [41] to name a few.…”

Section: Dynamic Partial Reconfigurationmentioning

confidence: 99%

A distributed memory, local configuration technique for re-configurable logic designs

Beasley¹

2020

Preprint

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The use and location of memory in integrated circuits plays a key factor in their performance. Memory requires large physical area, access times limit overall system performance and connectivity can result in large fan-out. Modern FPGA systems and ASICs contain an area of memory used to set the operation of the device from a series of commands set by a host. Implementing these settings registers requires a level of care otherwise the resulting implementation can result in a number of large fan-out nets that consume valuable resources complicating the placement of timing critical pathways. This paper presents an architecture for implementing and programming these settings registers in a distributed method across an FPGA and how the presented architecture works in both clock-domain crossing and dynamic partial re-configuration applications. The design is compared to that of a 'global' settings register architecture. We implement the architectures using Intel FPGAs Quartus Prime software targeting an Intel FPGA Cyclone V. It is shown that the distributed memory architecture has a smaller resource cost (as small as 25% of the ALMs and 20% of the registers) compared to the global memory architectures.

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“…However, in spite of the fact that DPR meets SDR requirements with a better performance in terms of power consumption and resources [8], it is not included in fast prototyping MBD commercial flows. This enforces developers to combine these technologies manually, which is translated in an increased complexity, cost and iteration time for embedded tests.…”

Section: Introductionmentioning

confidence: 99%