A Software-Defined Always-On System With 57–75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC

Wang, Zhixuan; Zhang, Hao; Zhang, Yihan; Shen, Linxiao; Ru, Jiayoon; Fan, Haitao; Tan, Zhichao; Wang, Yangyuan; Ye, Le; Huang, Ru

doi:10.1109/jssc.2021.3074636

Cited by 14 publications

(8 citation statements)

References 25 publications

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“…Figure 4 illustrates the switching control approach employed by the 6-bit DAC. When CLK_DAC is at a logic high level, the backplanes of the 6-bit DAC are connected to V ref or V SS based on the high six-bit output signals D [5]-D [10] of the 11-bit SAR ADC. According to the timing diagram shown in Figure 5, the SAR ADC must complete the conversion within a single cycle.…”

Section: System Architecture and Operationmentioning

confidence: 99%

“…Its circuit comprises an input ch scaling circuit, comparator, and up/down counter. In contrast, a floating-window-ty ADC [5] is depicted in Figure 2b and features a DAC, comparator, and up/down cou In classic LC ADC designs, there is often a tradeoff between accuracy, power cons tion, and speed. The architecture of a conventional LC ADC is illustrated in Figure 2a,b.…”

Section: Introductionmentioning

confidence: 99%

“…Refs. [5,13] presented an LC-ADC with an asynchronous pipelined and event-driven architecture. It consumes only 41 nW of standby power owing to the wake-up function and demonstrates a higher energy economy of level cross-sampling in sparse events.…”

Section: Introductionmentioning

confidence: 99%

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A 0.49–4.34 μW LC-SAR Hybrid ADC with a 10.85-Bit ENOB and 20 KS/s Bandwidth

Tang,

Xu,

et al. 2024

Electronics

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This paper presents a level-crossing successive-approximation-register (LC-SAR) hybrid analog-to-digital converter (ADC) that combines an LC ADC with an SAR ADC, which may be used for Internet of Things (IoT) random sparse event scenarios. The sampling frequency of a traditional LC ADC is usually proportional to the maximum instantaneous rate of change of the input signal; therefore, a higher input signal frequency inevitably leads to higher system power consumption. However, the proposed hybrid ADC uses the input level difference between the two moments before and after level-crossing detection, thereby ensuring a higher conversion precision and lower power consumption, even at higher input signal frequencies. Compared with traditional LC ADC or SAR ADC, the proposed hybrid ADC combines the ultralow-power advantage of LC ADC with the high-precision advantage of SAR ADC in converting IoT data with sparse characteristics such as ECG, EEG, and brain potential. The LC-SAR hybrid ADC is designed with a 0.18 μm CMOS process and consumes 4.34 μW at a 1.8 V supply voltage, achieving an SNDR of 67.41 dB and a bandwidth of 20 kHz. The spectrum analysis result was 10.85 ENOB when the input sinusoidal signal was 14.975 kHz. When inputted with an ECG signal, the system power consumption was as low as 0.49 μW. Furthermore, the proposed hybrid ADC obtained a good figure of merit, with FoMw and FoMs reaching 58.8 fJ/conv.steps and 164 dB, respectively. Compared to a conventional uniform sampling ADC, approximately 80% of the power savings and an 8x compression ratio can be achieved in physiological signal acquisition applications.

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Section: System Architecture and Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 0.49–4.34 μW LC-SAR Hybrid ADC with a 10.85-Bit ENOB and 20 KS/s Bandwidth

Tang,

Xu,

et al. 2024

Electronics

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“…A distance of more than 500 m has been achieved for heavy tracked vehicle recognition. A 75 nW wake-up chip is reported to detect heart rate, epilepsy, and keyword, which can be further applied to acoustic wake-up microsystems for practical use, as shown in Figure 17 g [ 67 ]. A wake-up chip for ultrasonic signal detection is reported with a smaller size of 14.5 mm 2 , as shown in Figure 17 h [ 68 ].…”

Section: System Wake-up Architecturementioning

confidence: 99%

Acoustic Wake-Up Technology for Microsystems: A Review

Yang

Zhao

2023

Micromachines

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Microsystems with capabilities of acoustic signal perception and recognition are widely used in unattended monitoring applications. In order to realize long-term and large-scale monitoring, microsystems with ultra-low power consumption are always required. Acoustic wake-up is one of the solutions to effectively reduce the power consumption of microsystems, especially for monitoring sparse events. This paper presents a review of acoustic wake-up technologies for microsystems. Acoustic sensing, acoustic recognition, and system working mode switching are the basis for constructing acoustic wake-up microsystems. First, state-of-the-art MEMS acoustic transducers suitable for acoustic wake-up microsystems are investigated, including MEMS microphones, MEMS hydrophones, and MEMS acoustic switches. Acoustic transducers with low power consumption, high sensitivity, low noise, and small size are attributes needed by the acoustic wake-up microsystem. Next, acoustic features and acoustic classification algorithms for target and event recognition are studied and summarized. More acoustic features and more computation are generally required to achieve better recognition performance while consuming more power. After that, four different system wake-up architectures are summarized. Acoustic wake-up microsystems with absolutely zero power consumption in sleep mode can be realized in the architecture of zero-power recognition and zero-power sleep. Applications of acoustic wake-up microsystems are then elaborated, which are closely related to scientific research and our daily life. Finally, challenges and future research directions of acoustic wake-up microsystems are elaborated. With breakthroughs in software and hardware technologies, acoustic wake-up microsystems can be deployed for ultra-long-term and ultra-large-scale use in various fields, and play important roles in the Internet of Things.

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“…Spending significant time and energy on easy-to-classify samples in long-term monitoring scenarios is particularly problematic for ECG processors. Consequently, recent studies have focused on the development of hybrid multi-stage wake-up architectures [30][31][32]. These systems feature:…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient ECG Processor Based on HDWT and a Hybrid Classifier for Arrhythmia Detection

Deng,

Ma,

Yang

et al. 2023

Applied Sciences

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Cardiac arrhythmia (CA) is a severe cardiac disorder that results in a significant number of fatalities worldwide each year. Conventional electrocardiography (ECG) devices are often unable to detect arrhythmia symptoms during patients’ hospital visits due to their intermittent nature. This paper presents a wearable ECG processor for cardiac arrhythmia (CA) detection. The processor utilizes a Hilbert transform-based R-peak detection engine for R-peak detection, a Haar discrete wavelet transform (HDWT) unit for feature extraction, and a Hybrid ECG classifier that combines linear methods and Non-Linear Support Vector Machines (NLSVM) classifiers to distinguish between normal and abnormal heartbeats. The processor is fabricated by the CMOS 110 nm process with an area of 1.34 mm2 and validated with the MIT_BIH Database. The whole design consumes 4.08 μW with an average classification accuracy of 97.34%.

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A Software-Defined Always-On System With 57–75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC

Cited by 14 publications

References 25 publications

A 0.49–4.34 μW LC-SAR Hybrid ADC with a 10.85-Bit ENOB and 20 KS/s Bandwidth

A 0.49–4.34 μW LC-SAR Hybrid ADC with a 10.85-Bit ENOB and 20 KS/s Bandwidth

Acoustic Wake-Up Technology for Microsystems: A Review

An Energy-Efficient ECG Processor Based on HDWT and a Hybrid Classifier for Arrhythmia Detection

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