2014 Sixth International Conference on Intelligent Human-Machine Systems and Cybernetics 2014
DOI: 10.1109/ihmsc.2014.179
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A SoC Design and Implementation of H.264 Video Encoding System Based on FPGA

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Cited by 2 publications
(3 citation statements)
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“…This is enabled by integrating and utilizing higher camera resolution data to detect the object, update system data, track the object motion and extract the object distance and dimensional data in an efficient way. By using a higher resolution camera scan to augmented a lower resolution system, the data loss and resultant reduction in accuracy due to compression techniques like averaging can be avoided to provide improved object tracking performance [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20].…”
Section: Original Contributionmentioning
confidence: 99%
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“…This is enabled by integrating and utilizing higher camera resolution data to detect the object, update system data, track the object motion and extract the object distance and dimensional data in an efficient way. By using a higher resolution camera scan to augmented a lower resolution system, the data loss and resultant reduction in accuracy due to compression techniques like averaging can be avoided to provide improved object tracking performance [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20].…”
Section: Original Contributionmentioning
confidence: 99%
“…The included object tracking and navigation methods for vehicles and mobile robots. The examination embedded system and its direct application were also reviewed [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31].…”
Section: Literature Classificationmentioning
confidence: 99%
“…Although this option offers good performance in terms of compression ratedistortion ratio, it also presents coarse drawbacks in order to be implemented on hardware, such as a complex architecture (specially the inter-prediction stage, where motion estimation is computed), preventing its implementation on hardware resources available on-board satellites [8], or an imprecise behaviour for lossless compression, among others. Different works are available in the state-of-the-art about FPGA implementations of the H.264 encoder, but focusing in particular stages whose performance is critical, such as motion estimation [9], [10], [11], [12], the intra-prediction [13], [14], quantization [15] or the encoding [16], [17]. A full hardware implementation of the H.264 encoder in baseline profile is presented in [18], consuming the 89% of slices available in a Xilinx XC6VLX240T FPGA.…”
Section: Introductionmentioning
confidence: 99%