A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories

Wang, Qianqian; Liu, Fei; Huang, Cece; Li, Qianhui; Huo, Zongliang

doi:10.1109/tvlsi.2021.3113980

Cited by 2 publications

(1 citation statement)

References 14 publications

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“…Firstly, excessive ripple voltage on selected WL will cause worse threshold voltage distribution and degrade flash memory reliability [12,13]. Consequently, various advanced pump structures and regulation techniques are applied to reduce ripple [14,15,16,17,18]. Secondly, for most portable products, power consumption is an important performance needed to be concerned.…”

Section: Introductionmentioning

confidence: 99%

A high-performance wordline voltage-generating system for low-power low-voltage flash memory

Zhou

Yan

Ming

2023

IEICE Electron. Express

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Wordline (WL) voltage-generating system is a crucial block in flash memory. It generates a voltage higher than the supply voltage for reading, programming and erasing in flash memory. However, operation accuracy is deteriorated by the excessive overshoot and ripple voltage. Moreover, current consumption in standby mode shortens the life of memory. The paper presents a high-performance wordline voltagegenerating system in 55nm CMOS technology. In active mode, a variable stage and frequency charge pump system is proposed to suppress overshoot and ripple of WL voltage (VWL) when the supply voltage ranges from 1.5 V to 2.1 V. To cut down standby current, an ultra-low power voltage reference circuit operating in subthreshold region is introduced. When recovering from standby mode, a standby recovery management circuit is utilized to minimize WL voltage setup time. The ripple voltage is 3 mV at 30 pF load with 20 MHz pumping frequency in active mode in post-simulation. The WL voltage setup time when recovery from standby mode is equal to 13.7 ns, even though the average standby current is less than 0.98 μA typically.

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Section: Introductionmentioning

confidence: 99%

A high-performance wordline voltage-generating system for low-power low-voltage flash memory

Zhou

Yan

Ming

2023

IEICE Electron. Express

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Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement

Tian,

Tang,

et al. 2024

ACM Trans. Des. Autom. Electron. Syst.

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Considering 3D NAND flash has a new property of process variation (PV) , which causes different raw bit error rates (RBER) among different layers of the flash block. This paper builds a mathematical model for estimating the retention errors of flash cells, by considering the factor of layer-to-layer PV in 3D NAND flash memory, as well as the factors of program/erase (P/E) cycle and retention time of data. Then, it proposes classifying the layers of flash block in 3D NAND flash memory into profitable and unprofitable categories, according to the error correction overhead. After understanding the retention error variation of different layers in 3D NAND flash, we design a mechanism of data placement, which maps the write data onto a suitable layer of flash block, according to the data hotness and the error correction overhead of layers, to boost read performance of 3D NAND flash. The experimental results demonstrate that our proposed retention error estimation model can yield a R 2 value of 0.966 on average, verifying the accuracy of the model. Based on the estimated retention error rates of layers, the proposed data placement mechanism can noticeably reduce the read latency by 29.8 % on average, compared with state-of-the-art methods against retention errors for 3D NAND flash memory.

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A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories

Cited by 2 publications

References 14 publications

A high-performance wordline voltage-generating system for low-power low-voltage flash memory

A high-performance wordline voltage-generating system for low-power low-voltage flash memory

Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement

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