A small fully digital open‐loop clock and data recovery circuit for wired BANs

Derogarian, Fardin; Ferreira, Joao Canas; Tavares, Vítor Grade

doi:10.1002/cta.2092

Cited by 2 publications

(3 citation statements)

References 28 publications

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“…The signals on the lines between the nodes were observed and measured with a digital oscilloscope. The results of signal quality and performance of both clock and time synchronization are presented separately in [6]- [8].…”

Section: Resultsmentioning

confidence: 99%

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A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems

Miyandoab

Ferreira

Tavares

et al. 2020

IEEE/ACM Trans. Networking

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A multifunctional router IC to be included in the nodes of a wearable body sensor network is described and evaluated. The router targets different application scenarios, especially those including tens of sensors, embedded into textile materials and with high data-rate communication demands. The router IC supports two different functionality sets, one for sensor nodes and another for the base node, both based on the same circuit module. The nodes are connected to each other by means of woven thick conductive yarns forming a mesh topology with the base node at the center. From the standpoint of the network, each sensor node is a four port router capable of handling packets from destination nodes to the base node, with sufficient redundant paths. The adopted hybrid circuit and packet switching scheme significantly improve network performance in terms of end-to-end delay, throughput and power consumption. The IC also implements a highly precise, sub-microsecond one-way time synchronization protocol which is used for time stamping the acquired data. The communication module was implemented in a 4-metal, 0.35 µm CMOS technology. The maximum data rate of the system is 35 Mbps while supporting up to 250 sensors, which exceeds current BAN applications scenarios.

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Section: Resultsmentioning

confidence: 99%

“…Many CDR methods have been designed and discussed in the literature [22]- [24]. In [8], an open-loop, low-complexity, very small size, fast-lock synchronization circuit for clock and data recovery in wearable systems is proposed, which is also utilized in the current IC.…”

Section: A Clock Synchronization and Data Recoverymentioning

confidence: 99%

A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems

Miyandoab

Ferreira

Tavares

et al. 2020

IEEE/ACM Trans. Networking

View full text Add to dashboard Cite

show abstract

“…The proposed model is analyzed in terms of visual perception and PSNR values. Synchronization with open loop and low complexity procedure is designed using 350‐nm CMOS technology in Derogarian et al It has an inverted decoder with nonreturn to zero logic which makes the receiver clock in phase with incoming signal. This method generates robustly a synchronous clock for data recovery.…”

Section: Overview Of Conventional Techniques For Viterbi Decodermentioning

confidence: 99%

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Radha

Shylu

Nagabushanam

2019

Circuit Theory & Apps

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Summary Viterbi decoder (VD) is the majority used decoder for convolutional codes which play a role in WLAN and WSN applications. The trellis in VD needs proper analysis to calculate the metric at each stage to obtain a shortest path from every state to the next state. Existing techniques in VD design are namely (a) pipelined architecture, (b) modular ACS and buffers technique, and (c) quasi cyclic trellis technique. The key challenge of the VD trellis circuit is to attain high throughput and better latency performance with low power consumption without affecting hardware complexity of VD. This paper presents several of conventional methods used in VD. We also proposed a new method for VD with K the constraint length as multiple of M, the radix in trellis to calculate the shortest survival path to travel in trellis. The proposed VD is simulated using Xilinx. Use of a trace back approach in the proposed Viterbi decoder with capacitive and resistive feedback yields better throughput, latency, and power consumption with respect to other techniques. The static power outputs obtained in RE, shift update, and selective update methods using Libero IDE are also compared.

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A small fully digital open‐loop clock and data recovery circuit for wired BANs

Cited by 2 publications

References 28 publications

A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems

A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

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