A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit

Abstract

This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz.

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain

“…With the arrival of big data era, NAND Flash memory with large capacity, high bandwidth and high reliability is widely used, and the data transmission rate between NAND Flash memory and controller is also increasing [1,2,3,4,5,6,7,8,9,10,11,12]. Data transmission between NAND Flash memory and controller is realized by utilizing Non-Volatile double data rate (NV-DDR) interface which requires sampling data at the positive and negative edge of interface clock [1,2,3,4,5,6,7].…”

“…The duty cycle of interface clock may be seriously distorted due to mismatches between pull-up and pull-down clock driver in the transmission path, lead to the bit error rate increase at high frequency. Therefore, NAND Flash memory needs a duty cycle corrector (DCC) to shape duty cycle of clock to 50% [1,2,3,4,5,6,7,8] , and DCC circuits with smaller correction accuracy have the more obvious advantage.…”