A sliding window scheme for accurate clock mesh analysis

Abstract

Mesh architectures are used for distributing critical global signals on a chip such as clock and power/ground. The inherent redundancy created by loops present in the mesh smooths out undesirable variations between signal nodes spatially distributed over the chip. However, one outstanding problem with mesh architectures is the difficulty in analyzing them with sufficient accuracy. In this paper, we present a new sliding window-based scheme to analyze the latency in clock meshes. We show that for small meshes, our scheme comes within 1% of the SPICE simulation of the complete mesh with respect to clock latency. Our scheme is ideally suited for distributed-or grid-computing. We show large design instances where SPICE could not finish, whereas our scheme could complete the analysis in less than 2 hours.

Analysis of large clock meshes via Harmonic-weighted model order reduction and port sliding

“…For the port sliding scheme, we show the runtime and accuracy of the three different port sliding methods: driver merging, importance-weighted model reduction, combined driver merging and MOR. We also make comparison with the sliding window scheme [15]. The proposed algorithms have been implemented in C++.…”

“…For instance, in [11]- [13], techniques have been proposed to reduce the complexity of model order reduction by means of port compaction and merging. From a simulation perspective, spacial locality of power grid analysis has been observed in [14] and a sliding window approach is proposed to analyze clock meshes via divide-and-conquer in [15].…”

“…Although our port sliding scheme looks similar to the sliding window technique in [15], these two approaches are significantly different. In [15], a large mesh is heuristically divided into smaller partitions and then each partition is solved by completely neglecting circuit elements out side of the partition. The network partitioning is critical for controlling the accuracy, however, it is done completely based on heuristics.…”

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

“…Hence nodes which are far apart have less electrical impact on each other. From numerous simulations (on meshes of different sizes, with different window sizes), the authors in [11,12] prove that the delay calculated by the SWS at the clock sinks is always within 1 percent of the clock delay calculated by a complete simulation of the whole mesh modelled accurately. Since each segment of tree and stub has to be π-modelled (Fig.…”

“…In fact, the difficulty in simulating the clock mesh is one of the prominent reasons for its unpopularity when compared to the tree based clock distribution. The sliding window scheme ( [11,12]) is a method of simulating a big mesh by splitting the simulation task into smaller meshes called 'windows'. The wires connecting the sinks to the mesh are modelled accurately inside the window and approximately outside the window (Fig.…”