A six-port 30-GB/s nonblocking router component using point-to-point simultaneous bidirectional signaling for high-bandwidth interconnects

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

“…Combined application of both ideas enables a compact 0.34 mm design, resulting in a 34% reduction in router layout area as shown in Fig. 6(b), 26% fewer devices, 13% improvement in average power and one cycle latency reduction (from 6 to 5 cycles) over the router design [11] in [11] when ported and compared in the same 65-nm process [12]. Results from comparison are summarized in Table II.…”

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling

“…However, these links are unsuitable for mobile memory I/O interfaces for the following reasons: 1) using symmetric links between two similar devices, as opposed to the master/slave configuration in a memory interface, and 2) requiring extensive initialization time [1] ( 1000 clock cycles [1]), which becomes problematic to meet mobile DRAM I/O needs in switching between active, stand-by, self-refresh and power-down operation modes [1]. Simultaneous bidirectional (SBD) interconnect [9]- [11], has also been developed to facilitate increased aggregate memory bandwidth with simultaneous and bidirectional point-to-point communication links. However, such interconnect encounters challenges from reduced input signal noise margin due to increased number of voltage references and higher crosstalk and inter-symbol interference (ISI) due to the low-pass effects of the channel [11], which in either case degrades its bit-error rate (BER).…”

A True Full-Duplex IO (TFD-IO) With Background SI Cancellation for High-Density Interfaces

“…To achieve higher throughputs, the high-speed FD interconnects proposed/demonstrated recently have used hybrids with active circuits for interference suppression [15]- [28]. These hybrids effectively consist of one of the following: (i) a scaled replica generator with a subtractor [11]- [13], [21], [28]; (ii) a comparator with dynamic referencing [16], [20], [23]- [27]; (iii) a resistive or a capacitive bridge [21], [22]; (iv) a resistor-transconductor (R-gm) cell [17], [19]; and (v) a directional inverter/buffer (DIB) with weighted cancellation paths [29]. The main limitation in these schemes is that they do not account for the delay spread of the transmitted pulses that causes SI over multiple bit periods.…”