A single-loop approach to SIMD parallelization of 2D wavelet lifting

Kutil, Rade

doi:10.1109/pdp.2006.14

Cited by 22 publications

(10 citation statements)

References 19 publications

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“…Still, the amount of data transfer related to the auxiliary buffer is half of the entire column group, and this halves the amount of data transfer for the splitting step. We find that a similar idea is published in [24] for the lossy case. Loop fusion for the four lifting steps is described in the paper.…”

Section: Parallelization and Vectorization Of Dwt Based On The Data Dsupporting

confidence: 84%

Computing discrete transforms on the Cell Broadband Engine

2009

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Section: Parallelization and Vectorization Of Dwt Based On The Data Dsupporting

confidence: 84%

Computing discrete transforms on the Cell Broadband Engine

2009

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“…The amount of data transfer related to the auxiliary buffer is half of the entire column group, and this halves the amount of data transfer for the splitting step. We recently find that a similar idea is published in [7] for the lossy case. Loop fusion for the four lifting steps is described in the paper.…”

Section: Instructionsupporting

confidence: 72%

Optimizing JPEG2000 Still Image Encoding on the Cell Broadband Engine

Kang

Bader

2008

2008 37th International Conference on Parallel Processing

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“…SIMD vectorization of the 2-D DWT has been considered in [17]- [22]. Chaver et al [17] used SSE and the CDF-9/7 filter.…”

Section: Related Workmentioning

confidence: 99%

“…Kutil [22] has implemented the (9,7) lifting scheme using built-in SSE functions. He proposed a single loop approach to SIMD vectorization.…”

Section: Related Workmentioning

confidence: 99%

Implementing the 2-D Wavelet Transform on SIMD-Enhanced General-Purpose Processors

Shahbahrami

Juurlink

Vassiliadis

2008

IEEE Trans. Multimedia

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Abstract-The 2-D Discrete Wavelet Transform (DWT) consumes up to 68% of the JPEG2000 encoding time. In this paper, we develop efficient implementations of this important kernel on general-purpose processors (GPPs), in particular the Pentium 4 (P4). Efficient implementations of the 2-D DWT on the P4 must address three issues. First, the P4 suffers from a problem known as 64K aliasing, which can degrade performance by an order of magnitude. We propose two techniques to avoid 64K aliasing which improve performance by a factor of up to 4.20. Second, a straightforward implementation of vertical filtering incurs many cache misses. Cache performance can be improved by applying loop interchange, but there will still be many conflict misses if the filter length exceeds the cache associativity. Two methods are proposed to reduce the number of conflict misses which provide an additional performance improvement of up to 1.24. To show that these methods are general, results for the P3 and Opteron are also provided. Third, efficient implementations of the 2-D DWT must exploit the SIMD instructions supported by most GPPs, including the P4, and we present MMX and SSE implementations of horizontal and vertical filtering which provide a maximum speedup of 3.39 and 6.72, respectively.

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A single-loop approach to SIMD parallelization of 2D wavelet lifting

Abstract: Abstract

Cited by 22 publications

References 19 publications

Computing discrete transforms on the Cell Broadband Engine

Computing discrete transforms on the Cell Broadband Engine

Optimizing JPEG2000 Still Image Encoding on the Cell Broadband Engine

Implementing the 2-D Wavelet Transform on SIMD-Enhanced General-Purpose Processors

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