A single latch, high speed double-edge triggered flip-flop (DETFF)

Johnson, Thomas A.; Kourtev, Ivan S.

doi:10.1109/icecs.2001.957712

Cited by 20 publications

(16 citation statements)

References 6 publications

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“…The node is restored by I 2 through the nMOS (M 6 ) switch, but nMOS is a weak 1 switch, so as per switch property, it can restore the node up to V dd À2 V tn . This will be the case also for Johnson and Kourtev [14], Sung and Chang [15], and Wang [16], but they used a full swing XOR gate, so the corresponding node in those circuits is restored to V dd ÀV tn . As per the above discussion, if node y in Fig.…”

Section: Holding Periodmentioning

confidence: 99%

“…We further explored the possibility of reducing the power consumption and area of the DETFF proposed by Johnson and Kourtev [14], Sung and Chang [15], and Wang [16]. Our proposed DETFF circuit reduces the clock driver load by adopting a selective low swing XOR-gate {0 to (V dd À V t )}, …”

Section: Introductionmentioning

confidence: 99%

“…So we need a static DETFF that is power-efficient as well as areaefficient with high-speed performance. Johnson and Kourtev [14] introduced a simple and power-efficient static DETFF, as shown in Fig. 1 (a).…”

Section: Introductionmentioning

confidence: 99%

“…2. All the transistors in the design, including clock driver circuits (except those in the back-to-back inverter of Johnson and Kourtev [14]) were replaced by low-V t transistors, and a low swing driver was adapted to reduce the power consumption and to reduce the leakage current issue. Later this approach was modified again by Wang [16] as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Low-power and area-efficient 9-transistor double-edge triggered flip-flop

Muthukumar

Choi

2013

IEICE Electron. Express

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Double-edge triggered flip-flops offer a solution to clock power reduction by lowering the clock frequency and maintaining the same data rate. A compact 9-transistor double-edge triggered flip-flop for reducing flip-flop power is proposed. A combination of a selective swing-based partial transmission gate (TG) approach and multi-V t transistors is used to make it area and power-efficient. The selective swing-based transmission gate approach reduces the transistor count, and the selective use of low-V t transistors overcomes the effect of any intermediate low swing voltage levels in the circuit due to a partial TG approach. Low transistor count reduces capacitive load of the dynamic power component, and selective use of low-V t transistors improves circuit performance as well as reduces power-delay product. The proposed circuit is implemented in the Samsung 130 nm 1P6M Multi-V t CMOS process technology and simulated for various PVT conditions. Results show that the power consumption of the circuit is reduced by 9.58% and energy reduced by 14.2% with a 5.12% improvement in speed for a slow process when compared to the previous techniques.

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Section: Holding Periodmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low-power and area-efficient 9-transistor double-edge triggered flip-flop

Muthukumar

Choi

2013

IEICE Electron. Express

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“…However, voltage scaling is associated with threshold voltage scaling which can cause the leakage power to increase exponentially [10]. By using dual-edge triggered flip-flops (DETFFs), the clock frequency can be significantly reduced-ideally, cut in half-while preserving the rate of data processing [11]. In many digital VLSI designs, the clock system that includes clock distribution network and flip-flops is one of the highest power consuming components and accounts for 30% to 60% of the total system power, out of which 90% is consumed by the flip-flops and the last branches of the clock distribution network that are driving the flip-flops [12].…”

mentioning

confidence: 99%

Power Efficient Dual Edge-Triggered Storage Design

Khan¹,

Hasan²

2017

IJET

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Abstract-In this work, four conventional most commonly referred master slave dual-edge-triggered storage designs are analyzed. The power efficient master slave dual-edge-triggered storage design is also proposed. A detailed comparison of the existing and proposed designs is presented in this work. All simulations are performed on TSpice using BSIM models in 130 nm process node. The simulation results show that the proposed design has the least power consumption for all data patterns, all supply voltages and all clock frequencies among all the discussed designs and has up to 97.41% lesser power consumption than existing designs. The proposed design has lesser PDP than all existing designs and has up to 97.63% improvement in PDP. The design has improvements in terms of power dissipation and PDP with reduced silicon area. The proposed design is suitable for low power applications of all data patterns and is also suitable for low area applications.Keyword -Edge triggered, Pass Transistor, Parasitic capacitance, propagation delay, clocked transistor I. INTRODUCTION The rapid scaling of silicon technology has enabled designers to integrate millions and even billions of transistors into a single chip. However, while the performance increases due to scaling, the power density increases substantially every generation due to higher integration density. So, the need for power-efficient design techniques has grown considerably [1]- [3]. The latest advances in mobile battery-powered devices have set new goals in digital VLSI design. These devices require high speed and low power consumption. So, the low power design is must for the applications operated by batteries such as pocket calculators, wrist watches, mobile phones, laptops etc. It is important to prolong the battery life as much as possible [4]- [8]. High power dissipation of a SoC will not only increase its system costs but also affect the product lifetime and reliability. Minimizing power dissipation increases lifetime and reliability of the circuit [9].Voltage scaling is the most effective way to decrease power consumption, since power is proportional to the square of the supply voltage. However, voltage scaling is associated with threshold voltage scaling which can cause the leakage power to increase exponentially [10]. By using dual-edge triggered flip-flops (DETFFs), the clock frequency can be significantly reduced-ideally, cut in half-while preserving the rate of data processing [11]. In many digital VLSI designs, the clock system that includes clock distribution network and flip-flops is one of the highest power consuming components and accounts for 30% to 60% of the total system power, out of which 90% is consumed by the flip-flops and the last branches of the clock distribution network that are driving the flip-flops [12]. So using lower clock frequency may translate into considerable power savings.Flip-flops thus contribute a significant portion of the chip area and power consumption to the overall system design. Therefore, it is imperative to carefully de...

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Energy-Efficient Double-Edge Triggered Flip-Flop

Wang

Chang

Shen

2010

J Sign Process Syst

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This paper presents a novel design for a double-edge triggered flip-flop (DETFF). A detailed analysis of the transistors used in the DETFF is carried out to determine the critical path. Therefore, the proposed DETFF employs low-V th transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-V th transistors can be resolved simultaneously. Therefore, the proposed DETFF fully utilizes the multi-V th scheme provided by advanced CMOS processes without suffering from a large area penalty, slow clock frequency, and poor noise immunity. The proposed design is implemented using a typical 0.18-μm 1P6M CMOS process. The measurement results reveal that the proposed DETFF reduce the power-delay product by at lease 25% (i.e., dissipated energy).

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A single latch, high speed double-edge triggered flip-flop (DETFF)

Cited by 20 publications

References 6 publications

Low-power and area-efficient 9-transistor double-edge triggered flip-flop

Low-power and area-efficient 9-transistor double-edge triggered flip-flop

Power Efficient Dual Edge-Triggered Storage Design

Energy-Efficient Double-Edge Triggered Flip-Flop

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