A single chip universal cable set-top box/modem transceiver

D'Luna, L.; Tan, Loke Kun; Mueller, D.; Laskowski, J.; Cameron, K.; Lee, Jind-Yeh; Gee, D.; Monroe, J.; Law, H.-M.; Chang, J.; Wakayama, M.; Kwan, T.; Lin, Cheng Huang; Buchwald, A.; Kaylani, T.; Liu, Feng; Spieker, T.; Hawley, R.; Samueli, H.

doi:10.1109/isscc.1999.759278

Cited by 5 publications

(6 citation statements)

References 1 publication

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“…This corresponds to a maximum bit rate of 64.44 Mbits/s for 256-QAM signals. [31] n/a 4 → 64 5 MBaud SAG-DD Shen [27] 0.25 µm 4 → 256 10 MBaud CMA, DD Tan [28] 0.5 µm 4 → 256, 1024 7 MBaud S-LMS D'Luna [29] 0.35 µm 4 → 256 7 MBaud S-LMS Wu [30] 0. 6 The functionality and timing of the final design was verified at the gate-level using the output gate-level netlist and standard delay format files produced by Quartus II for NC-VHDL.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…A number of recent application-specific integrated circuits (ASIC) QAM demodulator designs have been implemented that incorporate blind [24][25][26][27] or trained adaptive equalizers [28][29][30], which are listed in Table 3. The symbol frequency of these implementations range from 5 to 10 MBaud, while the signal constellation ranges from 4-QAM to 1024-QAM.…”

Section: Comparisonsmentioning

confidence: 99%

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A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators

Banovic

Khalid

Abdel-Raheem

2007

Digital Signal Processing

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Section: Implementation Resultsmentioning

confidence: 99%

Section: Comparisonsmentioning

confidence: 99%

A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators

Banovic

Khalid

Abdel-Raheem

2007

Digital Signal Processing

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“…Therefore, dedicated ASIC implementation is the right choice for digital cable TV demodulator. [2][3][4][5][6][7][8] have proposed several chip implementations of QAM demodulators. [2] presents a QAM receiver integrated with 10-bit ADC (Analog to Digital Converter) and FEC (Feed-forward Error Coding) decoder, but it has several shortages, such as lacks the capability to direct sample the signal with 36M/44M IF, fixed sampling rate with 4x IF frequency, low carrier frequency offset acquisition range.…”

Section: Introductionmentioning

confidence: 99%

“…[3] introduces a QAM demodulator with carrier frequency offset range of 80KHz, which has relative large area and less integration level. [4] proposes a highly integrated QAM demodulator, but from the architecture of carrier recovery loop, it can be concluded that the carrier acquisition range is not very large. [5] introduces a VLSI architecture for blind QAM demodulator which use normal four-corner carrier recovery algorithm, [6] proposes a 64/256QAM demodulator with symbol rate up to 8M baud.…”

Section: Introductionmentioning

confidence: 99%

A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoder

Shen

Tian

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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A DVB-C/ITU J.83-A compliant QAM (Quadrature Amplitude Modulation) demodulator suitable for digital cable TV is proposed, which can support 4~256QAM with variable bit rate up to 80Mbps. It integrates a 10-bit 40MSPS ADC, (204,188) Reed-Solomon decoder as well as a convolutional interleaver. The chip is implemented in SMIC 0.25um CMOS technology with die size of 3.5x3.5 mm 2 . It features wide carrier offset acquisition range, robust demodulation algorithm and small circuit area.

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“…Final channel selection is done with the second IFfilter. After further amplification with a variable-gain IF-amplifier, the signal is fed to an A/D-converter and digital demodulator [2,3]. Double-conversion receiver architecture, depicted in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Broadband Double-Conversion RF Tuner

Stadius¹,

Malinen²,

Jarvio³

et al. 2005

Analog Integr Circ Sig Process

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A prototype design of upconverter and downconverter units for a double-conversion cable-modem RF tuner are presented. The upconverter upconverts a channel from 47-862 MHz input band to around 1575 MHz intermediate frequency. The image-reject downconverter shifts the channel to 36.125 MHz (EU) or to 43.75 MHz (US). The upconverter includes a variable-gain low-noise amplifier, a double-balanced mixer, a three-stage VCO bank for LO generation and a divide-by-two circuit for driving an external PLL. The downconverter includes a LNA, image-reject mixers in Hartley configuration, a 3-stage polyphase filter, an IF-amplifier and a SAW driver. For the second LO generation the circuit includes a 6-GHz on-chip VCO, a divide-by-four circuit for quadrature LO and a divide-by-16 for feeding an external PLL. Signal reversal switching in the LO buffer can be used for the selection of LSB/USB injection. All building blocks are presented in this paper and experimental results are given from the upconverter, downconverter, and RF tuner demonstrator including SAW filters with center frequencies at 1575 and 44 MHz. The circuits are fabricated in a 0.9-µm SiGe bipolar process.

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A single chip universal cable set-top box/modem transceiver

Cited by 5 publications

References 1 publication

A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators

A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators

A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoder

A Broadband Double-Conversion RF Tuner

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