A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection

Sasaki, Nobuo; Kimoto, K.; Moriyama, W.; Kikkawa, Takamaro

doi:10.1109/jssc.2008.2010982

Cited by 71 publications

(46 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table I compares the performances of the presented work with the state-of-the-art wireless high-speed data links. As shown in the table, the proposed transceiver has the lowest energy-per-bit value [33]- [36]. Comparing with [33], which uses on-chip antennas, the transmitting data rate is thirty times higher whereas the distance is about eighty times longer.…”

Section: Measurement Resultsmentioning

confidence: 98%

A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

Chen

Joo

Sayilir

et al. 2009

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-A 43-GHz wireless inter-chip data link including antennas, transmitters, and receivers is presented. The industry standard bonding wires are exploited to provide high efficiency and low-cost antennas. This type of antennas can provide an efficient horizontal communication which is hard to achieve using conventional on-chip antennas. The system uses binary amplitude shift keying (ASK) modulation to keep the design compact and power efficient. The transmitter includes a differential to single-ended modulator and a two-stage power amplifier (PA). The receiver includes a low-noise amplifier (LNA), pre-amplifiers, envelope detectors (ED), a variable gain amplifier (VGA), and a comparator. The chip is fabricated in 180-nm SiGe BiCMOS technology. With power-efficient transceivers and low-cost high-performance antennas, the implemented inter-chip link achieves bit-error rate (BER) around 10 8 for 6 Gb/s over a distance of 2 cm. The signal-to-noise ratio (SNR) of the recovered signal is about 24 dB with 18 ps of rms jitter. The transmitter and receiver consume 57 mW and 60 mW, respectively, including buffers. The bit energy efficiency excluding test buffers is 17 pJ/bit. The presented work shows the feasibility of a low power high data rate wireless inter-chip data link and wireless heterogeneous multi-chip networks.Index Terms-Bond-wire antenna, high-speed link, on-chip antenna, wirebond antenna, wireless inter-chip link, wireless transceiver.

show abstract

Section: Measurement Resultsmentioning

confidence: 98%

A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

Chen

Joo

Sayilir

et al. 2009

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…[31,37,40,67,69,[75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94]. Specifically, Table 2 compares the proposed design to [31,37,40,67,79,83] in terms of area, gain, HPBW and bandwidth. With respect to antennas in the sub-10 GHz domain [40,69], the area occupation of the antenna design in Section 3 is limited to about 0.6 mm 2 .…”

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

“…[78][79][80]. The UWB antenna design approach can provide high bandwidth, low power and short-range communication for WiNoCs.…”

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

“…However, the UWB-based antenna in Ref. [78][79][80], implemented in a 180 nm CMOS technology as a meander-type dipole antenna with a length of about 3 mm, and integrated in a complete on-chip transceiver, allows for a transmission range limited to 1 mm. The area occupation of the antenna in the layout of Ref.…”

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

“…The area occupation of the antenna in the layout of Ref. [79], including the feeding circuitry, is about 2 mm 2 , i.e., 4 mm × 0.5 mm. The short transmission range, compared with the current die area, would require multi-hop wireless communication across the chip, which makes it less efficient for a communication distance above 1 mm.…”

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

See 2 more Smart Citations

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Gutiérrez¹

2017

JLPEA

View full text Add to dashboard Cite

Abstract:To allow fast communication-at several Gb/s-of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

show abstract

Wireless Interchip Interconnects

Kikkawa

2012

Advanced Interconnects for ULSI Technology

Self Cite

View full text Add to dashboard Cite

IntroductionAccording to the scaling rule of metal-oxide-semiconductor (MOS) transistors in silicon large-scale integrated circuits (LSIs), both operating frequency and power consumption can be improved by reducing the feature sizes of MOS transistors, as shown in Table 15.1 [1]. A system on a chip (SOC) has been developed because it enables the highest packing density of scaled transistors for building an ultra-large-scale integrated circuit system (ULSI). However, the scaling of metal interconnects in an SOC deteriorates the performance of the LSI system because it increases resistance-capacitance (RC) time constants in the metal interconnects, as shown in Table 15.2 [2, 3]. To solve the RC signal delay problems for advanced CMOS technology, new materials such as copper (Cu) and low dielectric constant (low-k) interlayer dielectric films have been introduced [4, 5], as shown in Figure 15.1 (a). Figures 15.1 (b) and (c) are schematic diagrams of complementary MOS (CMOS) inverter circuits connected with a metal interconnect line and its equivalent circuit, respectively [2, 3]. The rise time T 90 % of the output digital signal is expressed aswhere R int , R tr , C int and C L are interconnect resistance, transistor output resistance, interconnect capacitance and load capacitance, respectively. Although the new materials can reduce

show abstract

A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection

Cited by 71 publications

References 14 publications

A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Wireless Interchip Interconnects

Contact Info

Product

Resources

About