A single-chip solution for interfacing transducers to sensor networks using FPGAs

Abstract

A virtual laboratory application requires sensors to be setup at different geographical locations but controlled centrally at a remote site. The sensors in such applications need to be physically small, consume low power and capable of local processing tasks facilitating mobility to spread the sensor network system in a vast geographic area. In this paper, we present the design of a low-cost smart sensor node developed using a reconfigurable Field-Programmable Gate Array (FPGA) that embeds all processing and communication functionalities based on IEEE 1451 family of standards. The single chip design facilitates increased speedup of processing due to interprocess communication taking place within the chip itself. Results indicate the stability and the performance of the proposed architecture at different baud rates.

Single Chip Solution with1-Wire Communication Protocol to Interface Digital Transducers to Sensor Networks

“…The oversampling scheme which is generated by dividing the system clock frequency devisor based (a) (b) on a mathematical calculation is used to extract the received data bit. We selected a baud rate of 9600 as it is widely used in such applications and works in experimental setups in a reliable manner [6]. All mandatory TEDSs for the sensor node are implemented using internally created memory cells with an 8 bit data in accordance with the IEEE 1451.0 standard [7].…”